MIPS 4Kc Cache Initialization

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I'm working a MIPS 4Kc-type chip from Broadcom. I'm having trouble with
the cache initialization function. My code is based entirely on the
code from the book _See Mips Run_. When I change_cp0_config (0x7, 3)
after the setupCache() call the board reboots. Similarly, linux crashes
doing its own initialization. Any ideas?

void setupCache () {
    register unsigned int addr, junk;

    write_32bit_cp0_register (CP0_TAGLO, 0);
    for (addr = KSEG0; addr < KSEG0 + 0x00002000; addr += 16) {
    for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16)
    for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16)
        junk = *((unsigned int *)addr);
    for (addr = KSEG0; addr < KSEG0 + 0x00001000; addr += 16)

One of the macros looks like so:
#define Index_Store_Tag_I(i)            \
    __asm__ __volatile__(            \
        "cache    0x08,0(%0)\n\t"        \
        : : "r" (i)            \



Re: MIPS 4Kc Cache Initialization
Quoted text here. Click to load it

Okay -- *sigh* change_cp0_config was jumping to address 0. Having said
that, I adjusted things a bit:

-> I'm loading the cache code to KSEG1. It runs fine.
-> I'm running a tight loop before and after to check the runtimes
against the timer. The loop is loaded in to KSEG0. The first loop runs
fine uncahced. Enable cache and function begins normally without a
crash (by printing 3 characters) but then dies in the loop?

Loop Without Cache:
xuMON> go
Running: 80010000

Loop With Cache:
xuMON> go
Running: 80010000


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