MCUs other than ARMs

I am very familiar with the various ARM MCU offerings. But I have a need for an MCU with 3 or more SPI ports which is not so easy to find in an ARM. There are a few, but they have higher power consumptions and that makes them poor choices for a battery powered app.

I don't have hard requirements yet, but I think 128 kB of Flash will do the job along with 16 kB of SRAM. I may need an I2C port and of course a number of I/O pins (yes, we still have to guess, but 30 should do the job).

So far the estimates have been done using the power figures for the AT91SAM7S devices which is about 100 mW. So I prefer to keep the MCU power consumption no higher than that. 3.3 volt I/O operation is required, but that is fairly obvious these days.

Are there any good MCUs that do not require support from overseas? I guess that is a silly question since most are supported from overseas these days. What company is not multinational anymore?

Reply to
rickman
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Are these master or slave SPIs ? That's a pretty strange mix, and you main hope finding one is going to be a vendor that includes SPI modes in their UARTs. I've seen some dual SPIs, and some with > 3 uarts, but 3 SPIs.... Normally, this would be a CPLD solution ?

-jg

Reply to
Jim Granville

A quick google spits up one : MC9S12DP256

Reply to
Jim Granville

Just my luck, the Freescale web site is down for maintanence. What did you search on to find this? Were there other hits?

Reply to
rickman

First one was "3 SPI ports" microcontroller which gave one hit, but I see "3 SPI port" microcontroller is slightly better, with 12 hits.

-jg

Reply to
Jim Granville

Don't know what processing power you require but any freescale processor that has one or more TPU or eTPU's can provide you with all the SPI's ports you could every want (one eTPU can be programmed to give you up to 8 SPI ports). But don't know if you need SPI to memory DMA, SPI chip selects, SPI speed, bi directional, etc, not enough info

Reply to
steve

We don't need a lot of processing power. But we do need to keep the operating power to a minimum. I can't access the Freescale site since it seems to be under maintanence at the moment. But from the other info I can get from

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I would guess that the Freescale ARM processors are pretty power hungry compared to the Atmel parts.

Reply to
rickman

I was thinking the 68HC16 devices

can't you just bit bang the SPI interface using the Atmel ARM chip? SPI is a very simple interface

Reply to
steve

Politics. Yes, I have no doubt that it could be done that way. But we have just about everyone in the company review designs and the janitor seems to be a stickler for using just the right MCU for a given application. I think he is the guy that keeps appearing in Dilbert.

At this point we don't know a lot about what this part of the design will have to do in software. But whatever we assign to it, we can be sure it will grow. The general rule here is to provide plenty of capacity for growth. That is why 128 kB is on the list of requirements. I don't see how we would ever use more than 32 kB considering what it is intended to do, but I am told that we will surely end up with ten times more SW than we bargained for.

Reply to
rickman

The ATmega1281 might work if you can use external SRAM. (You can run the USART in SPI Master mode)

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Ulf Samuelsson
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Reply to
Ulf Samuelsson

I looked at the document and I don't think this will do the job. I need three SPI slave ports. I could likely live with the 8 kB. I also need an SPI master port to control an LCD, but I expect I can do that in software without too much complaint from the SW people.

So the major requirement is 3 slave SPI ports. The secondary requirement is low power, with 100 mW a target (along with lower power at lower speed or duty cycle). The rest is negotialble.

Anyone work with a 3 SPI device?

Reply to
rickman

You'll have hard time with timing - the slave port timing is dictated by the master alone.

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Tauno Voipio
tauno voipio (at) iki fi
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Reply to
Tauno Voipio

The AT91SAM7A3 has two SPIs and I think there is a good chance that one of the SPI slaves can be implemented on the SAM7A3 SSC block

256 kB Flash and 32 kB SRAM, so it is a little bit of overkill.

What speed do you run the SPI(s) at?

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Ulf Samuelsson
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Reply to
Ulf Samuelsson

It still sounds like a CPLD task to me :)

If these are Byte 4 wire SPI slaves, without fancy FIFO needs (ie single byte transactions, SS controlled ), then a ATF1502BE CPLD looks very likely to do the task. That should (just) swallow a 3 Slave SPI to simple Parallel BUS interface. ( the 1504BE would allow a little buffering )

In any solution, you will need to ensure the uC can respond fast enough to avoid SPI overrun errors. That will depend on the spacing between incomming bytes.

-jg

Reply to
Jim Granville

That is an interesting idea, but where do I get the parallel bus and what if I don't have the space for a small CPLD? I won't even go into the crap I have to deal with to interface with the CPLD/FPGA people.

There are MCUs out there that have 3 SPI ports, so it would be redundant to use a CPLD. I know Motorola has some devices that should meet the requirements. I'll have to get in touch with the local FAE and see if they can recommend something. It would have been nice to use an ARM as we just recently started moving our designs away from 8 bit MCUs to ARM devices. But I have serious power constraints and the ARMs with 3 SPI ports use way too much power.

Reply to
rickman

...

AT91SAM7A3 draws too much power?

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Ulf Samuelsson
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Reply to
Ulf Samuelsson

Well, 3 SPI ports is 12 pins, no ?

Those are separate issues. ( Won't they let you design your own CPLDs ? )

.. but very few, which is why you started this thread ?

So there is no silver bullet/one chip/low power solution - that's embedded design for you :)

CPLDs can slave SPI with very low powers, as their SPI is a true shift register. All uC SPI slaves MUST be clocked higher (x4..x10) than the fastest incomming SPI_CK, whilst CPLD SPI slave has No Clock = Static Power, and on an ATF1502BE, that's ~2.4uA.

-jg

Reply to
Jim Granville

and here is another one ;)

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5V operation, up to 3 SPI ports, and a few other things as well....

Be interested in just how 'separate' those two cores are.

-jg

Reply to
Jim Granville

At 200 mW, yes, I think that is more power than I can afford. Of course we can use techniques to reduce that when the CPU is idle, but I don't like to start with more than a 50% figure unless I *know* the CPU loading up front. With the CPU using 100% more than the total board power budget, I don't think I can work with that.

How certain are you that the SSC will work in SPI slave mode. Is there an app note on this? The SPI speed is very slow at 100 kbps.

Reply to
rickman

The SSC is not an SPI, it is a shift register which can work in master or slave mode. In the slave mode, you have a clock input, and in promiscuous mode the SSC will shift in everything which is clocked. In other modes, it will read n bits, m clocks after the start of a framesync. The SSC has slave DMA support which the SPI doesn't have.

A good programmer can use his master SPI to communicate with the SSC.

On the Power issue, you can of course run the part at lower clock frequency to get what you want, the SAM7X also has dual SPI and SSC.

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Ulf Samuelsson
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Reply to
Ulf Samuelsson

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