Market size of new, non-legacy, 5V ICs ?

You are looking at the wrong data, go to page 8 of that datasheet, halfway there is a blue header '74HCT595'. The bottom half of page 8 gives the HCT specs: Vih=2.0V (min) Vil=0.8V (max) It wouldn't be 'TTL compatible' with Vih=3.15V.

Now you have.

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Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail) 

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Thanks.

That's a nice trend which I hope continues. Is there any similar move on the peripheral side of things ?

The thing which finally forced me to start moving to 3.3V was trying to interface to one too many sensors/LCD displays/SPI devices which were 3.3V only and are not 5V tolerant.

One of those SPI devices was Microchip's SPI RAM range, so that's why this new 5V capable series was such a surprise.

Simon.

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Good question!

I was indeed looking at the wrong part - I had mentally copied the table headers from "Recommended operating conditions" on page 7 onto the table below for the HC part rather than the temperature ranges.

As you and Stef pointed out, now I have found such a part.

I am pretty sure we looked at NXP (along with TI) when we were doing the project - I wonder why we didn't use it. (Even if I can't read datasheets properly, the others on the team would have read them too.) At least if we ever do another revision of the card, we can consider this chip.

David

it varies alot nxp datasheet for 74hct14 says max 147uA at Vin = Vcc-2.1 ON semi say 2.4mA at Vin = 2.4V !

-Lasse

In general you are right. I think the "logic" side of TTL is going away. The logic families seem to be primarily interface devices like buffers, tri-states and registers.

What do you do that doesn't use PLDs of some type?

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Rick

This particular application needed to control a lot of solid-state relays from a 3.3V microcontroller. A chain of serial in, parallel out shift registers on the SPI bus is ideal for this - it's easy to control from the microcontroller, and there are only 4 wires routed around the board with each shift register connected to a group of 8 outputs. The shift registers are small, cheap and reliable. The only annoying issue is the levels, since the solid-state relays need 5V - we needed level converters too (though it is possible that the nxp 74HCT595 would have worked - I can't remember why we didn't use it).

PLDs would be much more expensive, require programming (both development time and effort, and at production time we would need to burn in the program), require much more routing since it is centralised, and be less reliable (being more complex). And of course most PLDs are 3.3V maximum output, though they are generally very flexible about their inputs.

If this had been a bunch of different logic chips connected together such as for address decoding, then I'd agree that a PLD would be a good plan.

Hmm wonders what is so difficult

74AHCT585 VIH min 2V @ Vcc = 4.5V 74AHC595 VIH min 2.1V @ Vcc = 3V VIH = 3.85 @ Vcc = 5V

Actually seem to be OK for my uses anyway, plentiful available.

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Ok, that is exactly the sort of app that MSI was designed for. I agree an FPGA is more than you need, although I won't agree that it is *more* expensive. I'm not sure what they are charging for 595 chips these days, but most of this stuff is $0.25 or more. That's about parity for

8 of these and a 100 pin FPGA. Well, maybe the FPGA is a bit more at $3-$4, depends on quantity. The main limitation is the I/O voltage. I have not found an FPGA tolerant of 5 volt signals. I had to add two 24 pin Quickswitch parts as buffers to a design I did a while back. FPGA folks just don't feel there is market enough to take the hit in whatever they would need to take the hit in for 5 volt tolerant I/Os.

As to the programming in production, does that add much time or trouble? If your design is stable you can get Flash FPGAs or the Flash PROMs for regular FPGAs preprogrammed by your vendor.

Once you add a bit of programmable logic to a board, it can be surprising what you find for it to do.

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Rick

Thanks for the recommendation here - and perhaps I will consider programmable logic a bit more favourably in the future (we /did/ consider it on this board too). But the key points against progammable logic here are that it means extra steps in development, extra steps in production, it clumps all the I/O together in one place rather than having a nice easily routeable chain of parts on an SPI bus, and it means using a complex part (with potential bugs) rather than a clear and simple "it just works" solution.

Obviously there is lots more that can be done once you first have programmable logic on board. But the flexibility is not cost-free.

SiliconBlue's iCE65 _was_ 5V tolerant, so of course Lattice immediately killed it off when they bought the company.

-a

Yes, I sorely miss the iCE65, "Johnny we hardly knew Ye". It also had a much lower static current than the iCE40. But even in the low power/low price market there is only so much need for low static currents and 5 volt tolerance.

I recall getting price quotes of under $3 for 100 pin devices. At that price it would have been good enough to replace nearly any MSI logic on a board. You don't even have to program them as they will deliver them pre-programmed.

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Rick

Yeah, I guess those are long gone. Altera still has internal clamp diodes in larger MaxII CPLDs which makes them 5V tolerant. But only as long as you make sure the CPLD is powered and configured before any pin can go to 5V...

Actually it is the clamp diodes that makes them 5 volt *intolerant*. If you apply greater than Vdd the clamp diodes conduct and the two power supplies fight it out with the diode in the middle. Who do you think wins that battle?

I guess you are referring to adding a series resistor to limit the current. That works ok on inputs but on outputs it has to be a resistor pullup which has slew rate issues in fast designs.

When I talk about 5 volt tolerance, I mean putting 5 volts directly on the FPGA I/O pin. Without the clamp diode, as long as the gate oxide of the input will take 5 volts, the I/O pin will handle the drive. But the FPGA makers keep thinning the gate oxide and don't want to have a separate step in the process for a thicker I/O gate oxide layer. So it's "goodbye" to 5 volt tolerance.

Heck, I remember Xilinx was talking about doing away with 3.3 volt tolerance. They seem to think their primary markets were all transitioning to 2.5 and 1.8 volt busses for internal (to the board) signals. I guess they want to get the oxide layers down to a single atom thick.

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Rick

f r

I believe xilinx has had two different ways to do 5V "tolerance",

one is the series resistor clamping with the esd diode to the, usually, 3.3V io supply

the other didn't have an esd diode to the supply but instead a ~5V clamp to ground that was more like real 5V tolerance, it was for 5V pci I think

f e

if you want high speed and low price you need to go small, small means lower voltage

-Lasse

That is a kludge, and the part itself cannot properly be called 5V tolerant.

Even the ones that are ONLY 5V tolerant, when powered, are not properly 5V tolerant.

This is what the Logic market now does. After a brief flirtation with 3V only, LVC parts are properly 5V tolerant, and allow any Vcc conditions. They sometimes call this Ioff, and these parts use an avalanch FET structure as the ESD clamp.

That is true of the core logic, but almost every part above a moderate size these days, has a Core Vcc, and many have Multiple Oxide choices.

So the issue is mainly in the IO-Ring, and for FPGA vendors, who tend to be ns-obsessed, 5V is off their radar.

The uC and Logic vendors prove there is no technical or cost barrier, to offering 5V, with low voltage cores. They also understand it expands their market.

A possible FPGA compromise would be to have one IO bank 5V tolerant, - that would incur the small speed impact in one bank, but users can choose IO and it is rare you need ALL 5V tolerant, or ALL highest speed.

-jg

Unfortunately this doesn't work in the general case. The series resistor slows the rise time of the input significantly. This also does not address the issue with outputs at all.

A 5 volt clamp or a 3 volt clamp? If they used a 5 volt clamp that implies that 5 volts on the I/O pin is acceptable and that indeed is true 5 volt tolerance.

Lower voltage on the supply, but that is not the same as lower I/O voltages. There are any number of MCU makers who are providing chips with low core voltages for the newer process devices with 5 volt tolerance on the I/Os. So it can be done, you just need the *will* to do it. I believe Xilinx dropped 5 volt tolerance somewhere around

120-150 nm while many MCU makers are pumping out devices at the 90 nm process node which still have 5 volt tolerance.

Like I said, Xilinx sees 5 volt tolerance as not useful in their primary markets. The rest of us are just tag alongs in their eyes and don't influence their plans.

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Rick

would incur the small speed impact in one bank, but users can choose IO and it is rare you need ALL 5V tolerant, or ALL highest speed.

I don't think it is just the speed issue. I think 5 volt tolerance requires a thicker oxide which means separate process steps for the 5 volt tolerant transistors. I understand why the FPGA makers do what they do. I just don't like it.

Silicon Blue had the right idea in my opinion. They were going after a market niche for small devices at very low power dissipation. They felt

5 volt tolerance was not hard to do in small process geometries and low core voltages. Lattice clearly doesn't feel the need to retain this feature considering the costs. I just wish they would give me some packages I can actually use! 0.4 mm BGAs are not very user friendly.

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Rick

Ditto. I cannot understand why they do not have more packages that chase the CPLD business. (eg TQFP48, QFP44 etc )

-jg

CPLD business. (eg TQFP48, QFP44 etc )

I think it all comes down to volume. They are targeting the portable and cell phone markets where they need to fit the tiniest footprints. The rest of us are in the noise... But once they mature the product line perhaps they will come out with a few more packages.

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Rick