I posted about this issue a year ago, just revisiting.
I've been looking for the lowest power any external memory chip can dissipate per megabyte and access speed.
Low power SRAM is the first choice, but the estimated power for a constant series of bursts gets very expensive on power. Async SRAM takes longer to return, but should allow lower power.
I've seen some nice PSRAM chips at really low 'operating' wattages, under 10ma even. I dont know what the vendor's 'operating' wattage is, what percent of the time is the CE raised high etc? If their claims are true their chips are lower power than low power srams. Maybe its that all SRAM chips are now produced on older fabs than PSRAM (Cellular RAM) giving PSRAM the edge.
I was playing with the idea of taking high speed sram and playing with the signals so that the duration of CE being up is lower than is asserted by the controller, just shaving the up assertion time while the CPU is running much slower than the chips. The aim is really 4MByte for under 1ma@3.3V in normal constant usage. Maybe I should have a large array of small space srams and a CPLD to create many CE signals so only one small chip is asserted high. The target speed of access is really 1MHz to 10MHz depending on the power budget.
Suggestions needed from experts, how can I go lower power while trying to maintain about 10MIPS on an ARM LPC2000 or other ARM chips, possibly running Linux or eCos?