looking for new microcontroller

L.S.,

We are students at the University of Twente and we are doing a real-life case for a Dutch company. This company would like us to come up with newer (embedded) microcontrollers to replace the current ones used.

We are hoping to get any usable information of anyone here. Maybe someone has done comparable investigations or maybe someone could give us a hint to find more information. Below we will provide some information about the current microcontrollers and the conditions for a new controller.

*Current controllers: At the moment 8 and 16 bits microcontrollers, respectively the Philips 80552 (based on 8051) and the Philips XA, are used. These controllers provide a realtime machine control with a maximum response time of about 0,1 mSec and about 2000 events per second.

One of the current trends is the increasing use of C++ on the 16 bits controller, which demands a lot of processor capacity. Another important thing is the increase of number of events in newer machines to more than

10000 per second.

*Conditions for a new controller: We are trying to find a newer controller to cope with the trends specified above and (as many as possible of) the conditions stated below:

- Suitable for use with C++ (particularly in the lineary address area and with many data pointers);

- Availability of C++ cross-compilers and debug tools. E.g. GNU (no front-end C++ compiler);

- Usable with a RTOS (at the moment in use: CMX);

- Many I/O on the chip: o One or more I2c busses; o Multiple external interrupt inputs; o Two 8 or 10 bit AD converter/ DA converter or PWM .

- Preferably a small external bus, to avoid problems when routing prints and EMC problems.

- Possibly internal FLASH (minimal 1Mbyte) and/or RAM (minimal 256K). External is also acceptable. (at the moment in use: internal flash or OTP to place a "loader"-programme on board and to load a flash or monitor- programme);

- Cost-effective (maximum of about EUR20, to keep the price of the machines competitive).

Maybe someone can help us a little. Thanks in advance.

Kindest regards, René Bloemberg and Erwin Elling

Reply to
Erwin Elling
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One important consideration is that it's a lot easier to hire programmers than FPGA geeks.

There is a lot of good discussion in comp.arch.fpga.

General consensus is that if you can do it with a micro or DSP, that's probably cheaper/faster.

FPGAs are also tested at the factory. Just like CPUs and RAMs and every other chip made today.

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Reply to
Hal Murray

Have a look into NEC's V850 product family. You will find an overview of the devices at

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Prices for single unit quantities start at about 5 Euro for the most simple devices and reach about 20 Euro or a bit more for the higher end ones with large on-chip memories. I think that all your requirements are covered by some of the devices.

Michael

Reply to
Michael Krämer

That's only a 5x increase ? If you are used to, and using the 80C552, a good upgrade candidate for this is the new uPSD33xx family from STm

This has a turbo C52 core, 32KB RAM, 256KBF, 2 UARTS, PLD, ADC, and JTAG ISP and ISD.... Not sure how real they are, but your need does not sound urgent.

For higher Analog and Core performance, but less MAX RAM and FLASH, look at the Cygnal family.

You can also use the Dallas 87C550, as a reasonable 80C552 upgrade, in the near term.

-jg

Reply to
Jim Granville

I accept that there is verification of the design of the integrated system, but would functional and/or performance testing of each FPGA be required for each or batch of FPGA's? In software, the software engineer would devise unit tests to test the structural integrity of the code -- what does one do for FPGA designs?

With a CPU board using an off-the-shelf micro, the manufacturer has tested the micro. Can one assume the same level of testing has been performed on the libraries for a given FPGA?

I guess this is also a question regarding the correctness of the tools and whether the simulator faithfully reflects the timing & behaviour of the target system.

Ken.

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Reply to
Ken Lee

per second.

with many data pointers);

front-end C++ compiler);

and EMC problems.

machines competitive).

Hi guys,

First of all, 1 Mbyte is a tad too much to integrate on the same die as the CPU at the moment. I would have liked to recommend the AVR which provides a good performance boost an high integration. The AVR has an inherent 8 Mbyte code addressing range, but unfortunately there is no chip available with more than 128 kB internal flash.

256 kB Internal flash is on its way and maybe 512 kB in the future. The external address bus suipports 64 kB SRAM.

It has a C++ compilers Some real time OSes are available. Two Wire Interface which is compatible with I2C peripherals

1-8 interrupts depending on chip. Low cost.

Since it has

--------------------------------------------- The ARM cores is of course one of the most supported cores out there in the industry.

If you check out the Atmel ARM products, then the AT91M55800 seems to be fairly close to your requirements. There is no I2C, instead there is an SPI interface, which can be used to emulate I2C. It might be that SPI is acceptable when your end customer make the switch. It has plenty of I/O due to its 176 pin package. This can run at 33 MHz and give you 25 MIPS which should be OK for your requirements. To get this performance, you need to shadow your flash to fast SRAM. There are a large number of interrupts internally, all vecotred, using a reprogrammable vecotr table. The FIQ input allows VERY fast interrupts. The CPU jumps directly to the interrupt routine and 5 shadow registers are switched into the pipeline ´to save the time oit woudl take to puch and pop them in the interrupt routine. The interrupts have programmable priority so that you can easily nest interrupts according to Your needs.

8 x 10 bit ADC inputs to the chip. There are 6 x 16 bit timers with PWM. In additon there are two DAC outputs.

There should be NO problem whatsoever finding whatever compiler or operating system you want. The development board is pretty cheap. $250 for an evaluation board which can be programmed using GNU C++.

If you need higher speed, then there is the AT91FR40162. This is a 10 x 10 mm BGA package with

  • 66 MHz ARM7TDMI
  • 256 kB of internal 32 bit zero waitstate SRAM
  • 2 Mbyte of 70 ns Flash

If you run from the internal SRAM, then the part is 60 MIPS. If you run from the 2 Mbyte flash the part is about 10 MIPS:

Assuming the code can be divided into time critical parts and non time critical parts you can get very high system performance using this chip. It does not have a lot of peripherals, but if you connect the chip to a smaller AVR working as an I/O coprocessor, then I think you have a food combination.

If you really want high åperformance, then consider the AT91RM9200. This has an 180 MHz ARM9 with 16 kB instruction cache and 16 kB Datacache.

  • TWI (I2C compatible)
  • 120 I/O
  • Burst Flash cabability (120 MB / second max transfer rate)
  • 8 interrupts (including FIQ) and Multi Input Wakeup on all pins (120 interrupts).
  • Can run with 8 or 16 bit bus.
  • No internal flash , but a Boot ROM which will allow you to solder an unprogrammed flash to the board, and then load it through a UART or through USB.
  • No internal ADC, but again a small AVR can do the job.

All should dmeet the 20 Euro price.

The AT91 support is coming from Atmel France, so it should be in the same time zone. This is quite improtant since you do not have to stay up late, or wake up early to speak to the apps team.

The AT91 is contrary to many ARM based ASSPs a standard product with a long expected lifetime.

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share by my Employer Atmel Nordic AB
Reply to
Ulf Samuelsson

processors

but

We

It really all depends on what you need to implement which is so special. Complex PCBs do add a lot of cost, but you can get plenty of processor performance for $85. An AT91M40008 has 256 kB of internal SRAM and easily runs 60 MIPS. Can be had with 0.5/2/4 Mbyte Flash inside the same 10 x 10 mm BGA package. It can communicate with an FPGA using the DMA supported bit synchronous serial port running at maybe 15 Mbps for easy layout..

If you dont bond out the parallel bus, layout is a piece of cake. With it, "somewhat" more complex. Don't know what you do with the FPGA, but I think that fast SRAM was a killer in Your first design. SDRAM is so much less expensive.

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Best Regards,
Ulf Samuelsson   ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB
Reply to
Ulf Samuelsson

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