large FIFO buffer

20 MHz is not really high speed...

Get some fast SRAM and a CPLD/FPGA and do the FIFO by hand. There are Cypress Dual port memory available, but they are normally hard to get in low quantities. Well, digikey carries Cy7C009/019, but with a real proce tag...

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I agree you want to use an FPGA for this solution. Would be very simple. If you're doing research might look for A/D conversions as they are usually clocked into a FIFO for holding before processing.

Terry Bowman

Uwe B> > Hello all,

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What is reasonable price range??

Often these caches are SRAM/DRAM based using some of the memory of the hard drive or directly under ASIC control.

20MHz is not high speed for FIFOs consider looking at IDT for their synchronous and asynchronous devices. I do assume this burst data has some form of clock with it.

Has someone else has said a 1Mb(128KB) or 4Mb(512KB) SRAM part is easy to find and a PLD/FPGA to drive that will be fairly trivial. Especially as the output is slower and by the sounds of things could have its read delayed (registered), if necessary whilst in the middle of a write cycle.

--
Paul Carpenter          | paul@pcserviceselectronics.co.uk
    PC Services
              GNU H8 & mailing list info
             For those web sites you hate

Thanks for all of your help. The SRAM decision only slightly complicated the design, but reduces the price drastically(by a factor of 10 or more!)... just what I was looking for! :)

I'll have a microcontroller on board, so maybe I can bypass the CPLD/FPGA if I'm clever.

Thanks again.

Best Regards, Adam Kumpf

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Tom Woodrow

Adam Kumpf wrote:

Be careful trying to use the processor to do the same task as the FPGA described above. AN FPGA will typically have no latencey or delay in servicing the output and stuffing the FIFO. These delays are often times not guaranteed w/ a processor. If your processor can be doing anything else, which is likely, make certain it will get the data before the next piece of data is ready. This all depends on the context preemption latency of your processor (worse case) versus the data input speed.

Also, an FPGA could be used without SRAM in some cases depending on the size and depth of the data. This also depnds on the FPGA/CPLD used as well. If this is possible then it could be cheaper then using SRAM especially if the FPGA can used for other purposes.

Terry Bowman

reads

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drives

That is a good link also but

takes you to store where you can actually buy the products. I just bought a bunch of their FIFO chips.

Tom Woodrow