Jtag chain for IBM PPC 405EP and TI DSP TMS320C6711C

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Hello,

I am designing a board with IBM PPC 405EP and TI DSP TMS320C6711C. I
want put those devices in a single JTAG chain so that i can carry out
boundary scan as well do the emulation by having jumpers
appropriately.

But i have one problem with defining a initial state for nTRST signal.
In DSP it is pulled low internally and datasheet specifies not to put
a pull-up on this line. But PPC datasheet says to put a pull-up on
this line. Can anybody help me sort out this issue.

I had copied the references made in both datasheets below. Pls help...

TI Dsp
"The TMS320C6711/11B/11C/11D DSP requires that both nTRST and nRESET
resets be asserted upon power up to be properly initialized. While
nRESET initializes the DSP core, nTRST initializes the DSP's emulation
logic.Both resets are required for proper operation.
While both nTRST and nRESET need to be asserted upon power up, only
nRESET needs to be released for the DSP to boot properly. TRST may be
asserted indefinitely for normal operation, keeping the JTAG port
interface and DSP's emulation logic in the reset state.
nTRST only needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP's boundary scan
functionality.
For maximum reliability, the TMS320C6711/11B/11C/11D DSP includes an
internal pulldown (IPD) on the nTRST pin to ensure that TRST will
always be asserted upon power up and the DSP's internal emulation
logic will always be properly initialized.
JTAG controllers from Texas Instruments actively drive nTRST high.
However, some third-party JTAG controllers may not drive nTRST high
but expect the use of an external pullup resistor on nTRST.
When using this type of JTAG controller, assert nTRST to initialize
the DSP after powerup and externally drive nTRST high before
attempting any emulation or boundary scan operations. Following the
release of nRESET, the low-to-high transition of TRST must be "seen"
to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the
device for either Boundary Scan mode or Emulation mode."

IBM PPC 405EP
" nTRST on the PPC405 based processors shouldbe pulled up with a 10K
resistor. Also note that nTRST must be asserted low in response to a
power-on or system reset or else the processor may not boot reliably.
It is recommended that nTRST from the JTAG connector be logically ORed
with power-on reset of the board before being connected to nTRST on
the processor"

Pls suggest some solutions....

Re: Jtag chain for IBM PPC 405EP and TI DSP TMS320C6711C
Hello,

I am designing a board with IBM PPC 405EP and TI DSP TMS320C6711C. I
want put those devices in a single JTAG chain so that i can carry out
boundary scan as well do the emulation by having jumpers
appropriately.

But i have one problem with defining a initial state for nTRST signal.
In DSP it is pulled low internally and datasheet specifies not to put
a pull-up on this line. But PPC datasheet says to put a pull-up on
this line. Can anybody help me sort out this issue.

I had copied the references made in both datasheets below. Pls help...

TI Dsp
"The TMS320C6711/11B/11C/11D DSP requires that both nTRST and nRESET
resets be asserted upon power up to be properly initialized. While
nRESET initializes the DSP core, nTRST initializes the DSP's emulation
logic.Both resets are required for proper operation.
While both nTRST and nRESET need to be asserted upon power up, only
nRESET needs to be released for the DSP to boot properly. TRST may be
asserted indefinitely for normal operation, keeping the JTAG port
interface and DSP's emulation logic in the reset state.
nTRST only needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP's boundary scan
functionality.
For maximum reliability, the TMS320C6711/11B/11C/11D DSP includes an
internal pulldown (IPD) on the nTRST pin to ensure that TRST will
always be asserted upon power up and the DSP's internal emulation
logic will always be properly initialized.
JTAG controllers from Texas Instruments actively drive nTRST high.
However, some third-party JTAG controllers may not drive nTRST high
but expect the use of an external pullup resistor on nTRST.
When using this type of JTAG controller, assert nTRST to initialize
the DSP after powerup and externally drive nTRST high before
attempting any emulation or boundary scan operations. Following the
release of nRESET, the low-to-high transition of TRST must be "seen"
to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the
device for either Boundary Scan mode or Emulation mode."

IBM PPC 405EP
" nTRST on the PPC405 based processors shouldbe pulled up with a 10K
resistor. Also note that nTRST must be asserted low in response to a
power-on or system reset or else the processor may not boot reliably.
It is recommended that nTRST from the JTAG connector be logically ORed
with power-on reset of the board before being connected to nTRST on
the processor"

Pls suggest some solutions....

Re: Jtag chain for IBM PPC 405EP and TI DSP TMS320C6711C
snipped-for-privacy@myw.ltindia.com (gowda) wrote in message
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Sorry about the spelling and grammatical errors... ;-)

I guess this doesn't help too much, but I'd like to share some
experiences that I have had with TI TMS320C6000 platform and it's
BScan implementation.
 
I've been working with a design that has several TMS320C6416 devices,
PPC440 and some other BScan devices in a sigle chain for BScan
testing. For emulation purposes TI DSPs are separeted from the chain
(two DSPs/emulation chain). I won't go into more details about the
design, but some notes on the BScan functionality with TI320C6416 in
heterogenous environment, namly:

In order to get the darn DPSs into BScan mode you need to have
EMU[1:0] pins correctly set and the pins are not latched only by the
raising edge of _TRST, but prior to that at least one TCK pulse has to
be applied when _TRST is active i.e. low.

TMS-reset (max. 5 TCK pulses with TMS held high) of the test logic
(TAP-controller into test logic reset state) in the TI TMS320C6000
doesn't obviosly work unless the chip is first got into Boundary-Scan
mode.

_TRST should be pulled-up as it actually should be done also
internally on any  BScan component. The dot1 standard doesn't mandate
this, but in order to access the test logic even when external access
to the _TRST is missing due to a fault, there should be an internal
pull-up instead pull-down that would disable the usage of the test
logic. One could easily think, that pull-down would make the chip
functionally usable even if the external access was missing (which is
of course true). However, as there are means to test if the access is
there or not it is strognly advisable to assure that the test logic is
usable also when the _TRST pin would have e.g. an open fault.

Getting the TMS320C6000 chips into BScan mode with BScan tester might
require small additional logic. For instance Göpel tool doesn't have
active TCK when _TRST is asserted. This means that EMU[1:0] pins
doesn't become latched correctly. However, if I recall correctly the
tool from JTAG Technologies has the TCK running also when _TRST is
active, so most likely the TI DSPs would get into BScan mode w/o
problems.

It really is annoying that a company, which joined the JETAG (-> JTAG
after yanks came along) working group back in 1986 to come up with the
nice IEEE1149.1 standard, is now doing things a lot more difficult
than they should be...

Re: Jtag chain for IBM PPC 405EP and TI DSP TMS320C6711C
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Jeeze, could they make it any more complicated???  TI was one of the
original founders and promoters of JTAG boundary scan and JTAG
debugging.  But for some reason, they do a lousy job of making their
development tools easy to use with a boundary scan capable board.
Worse, none of the vendors seem to care if their parts can be debugged
with the part in a boundry scan chain.  

I have to suggest that you keep the two JTAG ports separate.  I looked
into this and that was the suggestion from everyone I spoke to in the
industry; chip vendors, debugger vendors and JTAG test tool vendors,
especially the JTAG test tool vendors.  I expect they would know best.
In the factory test, you can always use multiple test ports
simultaneously, or so I was told.  I eventually gave up on the idea
since my board has multiple power zones and it is too hard to bring it
up so all the parts can be tested together.  I am going to use on board
software to test the board at the factory.  

But it does sound to me like you can tie the two nTRST pins together and
let the TMS part generate the power on reset for the PPC.  I don't see
where it says if the PPC nTRST can be held low after power on reset.
They just say it has to be reset and you should use a pullup.  Actually,
it sounds to me like the PPC JTAG is not designed correctly.  What if
you are running a debugger that pulls nTRST high actively and you do a
system reset?  Will the PPC hang if the nTRST is not pulled low?  

--

Rick "rickman" Collins

snipped-for-privacy@XYarius.com
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