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November 12, 2004, 5:33 am

Hello All,
Can some body provudes me a detail application note on interfacing a
dual port SRAM ( ASYNCHRONOUS) withh FPGA or microprocessor.. I am
having some problems in generating control signals for the SRAM like
putting the data bus on high impedance state while making output
enable signal active.
Thanks
john
Can some body provudes me a detail application note on interfacing a
dual port SRAM ( ASYNCHRONOUS) withh FPGA or microprocessor.. I am
having some problems in generating control signals for the SRAM like
putting the data bus on high impedance state while making output
enable signal active.
Thanks
john
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