Interest in AVR+MSP430 "general purpose" proto board?

:)

In an earlier incarnation I was going to use a high-end FPGA, but it's just too complex for my book. I'm already wondering how I'll get it finished in time and in roughly the page limit required.

Reply to
larwe
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Yes FPGAs are complex things to learn, and the tools are large, and also a moving target.

CPLDs are simpler, and a good stepping stone; the tools are stable, and relatively easy to learn and even easier to run.

We have them setup to launch from a text editor, and single key compile/fit/simulate take 1-2 seconds. PGM is sub 10s.

-jg

Reply to
Jim Granville

Is the back of this part of the board free, in case you want to mount the SD socket on the back, rotated 180 degrees, so the SD card doesn't overlap?

Nice idea, BTW. Would be nice with a CPLD as Jim suggested.

Reply to
Clifford Heath

There are currently no footprints at all on the back of the board, partly because for cost reasons I'm only putting silkscreen on the top side. That's a pretty good idea, though.

All right, all right, what is with the CPLD? CPLD talk is not going to make it into my book, but just supposing I were to add it to this board, how would you want it wired? All the pins coming to headers, or half the I/Os going to a micro and the other half to a header?

Reply to
larwe

OK, here is one suggestion:

Wire 4 CPLD pins to the uC(s), as SPI SPI_DI SPI_DO SPI_SS SPI_CK

and some of the others can go to pin headers,

- you can work out from their names, what they are used for, and some header candidates :)

Pin Name Resource/Direction

43 on LCD_RWn Dge-- 44 on LCD_RS Dge-- 1 -- TDI INPUT 2 PT DB6 Dge-- 3 PT DB5 Dge-- 5 PT DB7 Dge-- 6 PT DB4 Dge-- 7 -- TMS INPUT 8 PT DB1 Dge-- 10 PT DB3 Dge-- 11 PT DB2 Dge-- 12 PT DB0 Dge-- 13 on LCD_E Tg-g- 14 -- SPI_DI INPUT 15 on SPI_DO C---- 32 -- TDO C---- 26 -- TCK INPUT 39 SPI_SS INPUT
Reply to
Jim Granville

Okay - I'm running a bit behind schedule, but not much; I'll be ordering boards this week, just not Monday. An updated schematic and component layout are posted at - this will be the permanent home for the project. I think I've incorporated everything except the CPLD; no room to fanout those I/Os on a 2-layer board [at least not with my mediocre routing skills].

Reply to
larwe

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