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I2C arbitration problems - how can I solve them

Hi,

I am currently working on an I2C interface (student project). The normal arbitration process seems to be clear for me but in some specific cases I have some problems. They are all related to the situation in which no one has won the arbitration after several bytes and one likes to generate a RESTART or a STOP while the other likes to continue to transmit.

  1. Assume that two masters access the bus at the same time, they start a write access to the same slave (no conflict detected) and they write the same data byte (no conflict detected). Now one master likes to STOP keeping SDA low and the other one likes to write a byte with MSB high. For sure, the second master detects a conflict but by standard, this master can continue to generate the clock until the end of the byte. When this master drives the clock line low before the master released SDA to generate the STOP, there will be no STOP on the bus. In worst case, the accessed slave will generate the ACK but gets no falling edge as the first master stops generating the clock after the transmitted byte.

Do you have any idea how to solve this?

  1. Assume that two masters access the bus at the same time, they start a write access to the same slave (no conflict detected) and they write the same data byte (no conflict detected). After that, master 1 likes to generate a RESTART while master 2 likes to continue by transmitting a data byte with MSB high.

It seems to me that also in this case, especially at the falling clock edge, problems can occur

Thanks for some hints, Kris

Reply to
kiwi
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The issues you raise are specifically addressed by the standard: Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C-bus. If it=92s possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isn=92t allowed between: =B7 A repeated START condition and a data bit =B7 A STOP condition and a data bit =B7 A repeated START condition and a STOP condition.

You'll either have to use a fixed transfer frame or ensure that arbitration is complete before the STOP or RESTART.

Reply to
Dingo

Thanks, Dingo.

I think that I now understand this passage from the standard. First I thought that "between" was meant in time, not at the same moment.

As it seems to me that completion of arbitration can not be guaranted (Both masters do the same before STOP/REPEATED START; e.g. both try to access an EEPROM), I have to ensure correct behaviour by a fixed transfer frame.

Reply to
kiwi

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