how to generate time delay

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What is the best way to generate a time delay in a waveform.

(I understand how I could use a monostable one-shot to create a pulse.
Then I suppose letting another signal trigger off the trailing edge of
this pulse.  But I cannot find a gate that triggers off the trailing
edge.)

Thanks in advance,
JD


Re: how to generate time delay
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You use inverters and differentiators to pick edges.

However one-shots are generally trouble.  Their periods drift, are
not precise in the first place, they can fail to trigger producing
an apparent crash, etc.  Safer methods are based on counters and
set/reset flip-flops.  Another technique is delay lines, which can
offer a graduated and coordinated series of delays.  They shine for
short times, the digital methods are best for longer times.

Differentiators are best built with straight logic.  Once the edge
has done its job, that signal comes back and cuts off the input.
For example:

                         +-----------------------> differentiated
                         |                         edge
                         |        flip-flop
 Signal >--+--------|\   |       ----------
           |        | o--+------|set\     Q|
           |    +---|/          |          |
           +----|---------------|reset\  Q\|----+
                |               +----------+    |
                +-------------------------------+

where the output of the nand gate is the differentiated version of
signal, on the rising edge, and inverted.  The flip flop is
actually two more nand gates.  The timing is naturally suited to
the logic it is built from.

--
Chuck F ( snipped-for-privacy@yahoo.com) ( snipped-for-privacy@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
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Re: how to generate time delay
On 30 Jun 2005 20:34:32 -0700, in comp.arch.embedded "John Douglas"

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use an inverter before the next monostable, or a 74LS123 which has
positive and negative triggering


martin

Re: how to generate time delay
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The 4528/4538 in 4000, and HCmos have choice of tigger-edges.
They also have reasonably precise delay defines.
Some companies also offer digital delay lines.
Clocked logic can do delays, but will quantize the output.

-jg


Re: how to generate time delay
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It depends what you're trying to do. Is it possible that your problem would
be better solved using synchronous logic?

Steve
http://www.fivetrees.com



Re: how to generate time delay
Thanks all for your input.   My intention is to generate a digital
pulse train using hardware logic chips.  (I am trying to create
hardware to read a ROM and load into RAM.  I am using the datasheet
from a 93C46 eeprom, as that is cheap and small and is all I will
need.)

I now understand there must be a better way than using one-shots to
generate a delay.
By further quantizing the signals by using various dividers off of a
single clock I have reduced my problem to one:  I still need a delay,
but now it can be treated as a phase offset.  So, if I have signal A
and signal B of the same frequency, how can I make signal B be out of
phase by 180 degrees.

(The differentation using the inverter shows two inputs to the
inverter.  I don't understand that?  And where is the clock into the
flip-flop?)

Thanks again,
JD


Re: how to generate time delay
By the way, I already have a routine to read the ROM from a PC parallel
port, but I want to do this from hardware as it will be a boot routine
for the start of a pseudo-CPU (and I'm learning as I go, BTW).

Thanks
JD


Re: how to generate time delay

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  Why not use a small CPLD, for this task ? - there are examples of
CPLDs for loading the RAM in FPGAs, from SPI memory.

  How are you building the psuedo-CPU ?

-jg


Re: how to generate time delay

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I'm doing the control unit first, most of which will be as a state
machine stored in an eeprom (which will first be loaded into ram).  But
I don't want to use a microcontroller.  I want the hardware circuitry
to load the serial eeprom to ram.  If I can accomplish that much, then
I'm sure I can design and build circuitry to step through the ram
addresses that will contain the state machine that acts as the control
unit.

I say "pseudo-CPU" because at this point I want to build merely the
control unit that will generate a set of desired waveforms.  Those
waveforms are fairly complex and I would not dream of doing them
without a micro-coded/micro-sequenced process using eprom.  However,
the waveforms to generate signals to read a serial eeprom into RAM are
much simpler and I am very close to a hardware design that I *think*
will work.  (I'm using very slow clock frequencies and making all my
divisions multiples of that freq.  Someone mentioned quantizing the
signal, I think thats what I am doing.)

IF examples existed for loading eprom into RAM and IF PLDs can be
programmed as easily as eproms apparently are (i.e. by hand or by PC
parallel port; a dedicated programmer is out of my budget range), then
maybe a PLD would be a possibility.  I'll look into that.

Thanks,
JD


Re: how to generate time delay
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Interesting project - how is the RAM set up: ?? Address Bits
and ?? Data bits for ?? Waveform(s) and ?? data bits to control/steer
the reading sequencer/stage machine. [fill in ??]

CPLDs start from ~32 macrocells = Flipflop+ ~5 Wide OR gate, in turn fed
by Wider AND logic. Thus you have appx 5 lines of Boolean Eqns per
macrocell.

So, for what you are trying to do, they are close to ideal.
Sounds like you need some state engines, and loadable Address Counters

In the simplest form, you write the Boolean equations, then compile to
JED, and download that into the ISP CPLD.
Probably easier than the Waveform file generation :)

Summary of CPLD suppliers (from memory):

Altera     MAX3000/7000    5V & 3V                     Quartus AHDL, & HDL
            MAX-II  -
AnaChip    PEELS & PLAs    5V & 3.3V [not ISP?]        WinPLACE SW
Atmel      ATF1502/04/08   LowPower 5V, 3.3V, ISP,     WinCUPL SW
Lattice    MACH4000 series Low power 3.3V/2,5V/1.8V    ispLever  ABEL & HDL
Xilinx     XC2Cxx Coolrunner  1.8V core, 3.3V io       ISE Webpack ABEL
& HDL

-jg


Re: how to generate time delay
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I don't understand the question. An inversion == 180 degrees.

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Two inputs to the inverter? I'm sorry, again I don't understand. Are you
sure it's an inverter and not a gate?

Steve
http://www.fivetrees.com



Re: how to generate time delay
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Please bear with me ...
Yes, 180 = inverter.  I was too hasty - I should have written 90
degrees rather than 180.

And to accomplish that, perhaps I could  send signal A through a
"divide by 2" freq divider.  Invert signal B and send it trough a
'divide by 2' freq divider.
Then B and A would be 90 degrees out of phase.  Is that a typical way
of doing this?

By the way, this is hobby/educational for me.  I've been reading IC
data sheets, Schaum's guides, college text books from libraries.  (Only
recently got into this.)  Is this the wrong forum for such a one?

Thanks,
JD


Re: how to generate time delay
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... snip ...
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You failed to bother to quote the article in question, and I am not
about to go to the trouble of making another ascii drawing.  If you
want help, why do you make it hard for anybody to supply it, by not
properly quoting?  There is no clock to a set/reset flip-flop.  A
nand gate expects at least two inputs.  If this stuff isn't clear I
think you are in the wrong business.

There have been many instructions here about using the fouled
google usenet interface.  Look around.  Make at least a minimal
effort yourself.  I am not in a good mood today.

--
Chuck F ( snipped-for-privacy@yahoo.com) ( snipped-for-privacy@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
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Re: how to generate time delay
Your ascii drawing shows 2 inputs to the inverter.  Thats what I was
referring to.


Re: how to generate time delay
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Why do you refuse to include adequate quotes?  Even on google it is
possible, see sig below.

Inverters have one input.  Nand gates have two or more.  It is hard
to draw semi-circles in ascii art, and the context should have
identified things.

--
"If you want to post a followup via groups.google.com, don't use
 the broken "Reply" link at the bottom of the article.  Click on
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