How to detect JTAG is connected or not

No way.

Why?

If you are a whiz, how come you need to ask such elementary questions? :-\

Steve

Don't know the OP's reason, but I wanted to do this too, for ARM7.

The reason was when trying to use the ARM debug communications channel, the program hangs if the JTAG is not connected. I was unable to find a way around this :(

I am by no means an expert on JTAG, but every time I have implemented a JTAG port on a circuit, I had to add pull-up and pull-down resistors. It isn't a software solution, which I gather is what you are after, but perhaps it is possible to monitor the state of these signal lines to determine if a device is connected.

"dspwhiz" ...

Use a pulldown on nTRST. That line will be driven high by the JTAG dongle when communicating. When the JTAG is not connected the line will be low (and the JTAG logic kept in reset, the prefered state).

Regards, Arie de Muynck

You've answered your own question.

Timeouts.

I am pretty sure that even an attempted write to the dcc locked up the program. There was no opportunity to do a "Timeout". Having said that, it was difficult to tell exactly what was going on without the debugger(!), and it was a few weeks ago now so I could be mistaken. Has anyone actually implemented this successfully? (I.e., a timeout on the debug communications channel that recovers from a missing debugger?)

"Arie de Muynck" ...

(and

P.S.: Connect the nTRST line also to a GPIO pin or other input of your system so it can be tested by the SW.

Regards, Arie de Muynck

thanks for the answers , I am a software guy, I went thru the docs but could not find a answers, I am using Au1550 processor and DM642.

For completeness, host board circuitry is required to maintain the JTAG port lines, although chip manufacturers may provide internal pull-ups / downs.

For devices with TRST ( I know it's active low, but that's it's name in the spec :) pull all other lines high, pull TRST low. (There are exceptions to this - the Intel PXA series has specific *ordinary* reset timing requirements applied to TRST).

For devices that do not have TRST:

Pull TCK ***LOW***, TDI, TMS high. The reason is the JTAG chain will enter test mode with TMS high on a rising edge of TCK. At system startup, depending on the board capacitances and the resistor sizes (to say nothing of chip innards), if both TCK and TMS are pulled to power, it is possible that normal startup can put the device in test mode (not a good thing [tm]).

Cheers

PeteS