How to design a bidirectional bus?

Hello,

I want to design an FPGA-based system which is controlled by PC host through USB-parallel interface (I use UM245R module from FTDI). My syste has several subsystems which have to have bidirectional data flow wit host. There are two things which are not clear for me and I would be glad to ge an advice on these. First, I do not understand how to organise communication through paralle output of the module. It has only 8 data lines, and for my system I wis to have 16-bit data and several additional lines for address bus. I wouldn't mind using the same bus as address bus and data bus but have n idea how to organise such bus. Second, what the interface between USB-parallel and FPGA has to be? whether it is separate PCB of some controller or it can be programmed o FPGA using VHDL? What is most natural way to do such things?

Reply to
Vagant
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One can also argue that USB has only 1 data line, how can the FTDI chip deal with 8 data lines.

It's just one more level of abstractions.

Use 1 data bit and 1 clock bit in FPGA to do USB.

Reply to
linnix

I took a quick look at the UM245R docs. It seems easy to use, not much different than using a UART (serial) chip. To write a byte to the chip, first check the TXE# status pin. You are only allowed to write a byte to the chip when this pin is LO. Your FPGA must put your byte onto the 8-bit bus and then drive the WR pin HI. See the doc's timing figures for more info. Note that you have to check TXE# prior to _every_ write. If you need to write 16-bits, then you will have to break that into 2 8-bit values. To read from the chip, first look at the RXF# pin. when that is LO, then you can read a byte from the chip, using the RD# pin. HTH

-Dave Pollum

Reply to
Dave Pollum

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