How to choose a firmware partner

IIRC RCA sold out to GE sold out to Honeywell sold out to Bull.

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Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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CBFalconer
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The older core memory had beads as large as a quarter of an inch across. IIRC, smaller coes means faster memory access.

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Guy Macon, Electronics Engineer & Project Manager for hire. 
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Guy Macon

Good grief. Make that KB, of course. Actually 32K 16-bit words. The early models were not byte addressable (except for the byte macros I wrote into the assembler.)

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Alan Balmer

... snip ...

Still should be. Grumph. Idiotic penny pinchers.

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Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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Reply to
CBFalconer

I am typing this on a Comopaq Prliant 5500R server that I got on eBay. Corrects all 1-bit errors, detects all 2-bit errors. Has 4 200Mhz Pentium Pro uPs with 1MB of cache on each one (I will upgrade to

500Mhz Pentium III Xeons when the price drops) 3GB of ECC RAM, and a twelve disk SCSI raid array with hotswap drives. All for under $500.
Reply to
Guy Macon

On April 7, 1964, the IBM System/360 announcement included systems with up to 512 Kbytes of main memory and optionally from 1 to 8 Mbytes of slower (8 us) "bulk core storage". First customer shipment was in

1965.

But several years earlier, IBM shipped their first computer that could directly address more than a megabyte.

The IBM 7030 Data Processing System (AKA "Stretch") had a typical configuration of six IBM 7302 core storage units, each of which was organized as 16384 words of 72 bits. It was the first computer to use ECC memory, so 64 of those bits were data. Each 7302 stored 128 Kbytes. The typical six-unit configuration stored 768 Kbytes, though the system could be expanded to 16 units for a total of 2 Mbytes.

First customer delivery of a 7030 was to Los Alamos Scientific Laboratories in April 1961, with customer acceptance in May 1961.

Note that the 7302 core storage unit was more commonly used in an organization of 32768 words of 36 bits, as used on the 7090, 7094, and perhaps other machines.

Early 7302 core storage units were oil-filled, but later ones (7302A?) were air-cooled.

Reply to
Eric Smith

64-bits is 8 bytes. 262,000 * 8 = 2,096,000 bytes per bank. 2 banks would be 4,192,000 bytes. Did I miss something?

Best Wishes

Reply to
Jeff Fox

stuff

now, or

GE was long out of the picture before Bull took over from Honeywell. Most of the conversion from GE to Honeywell involved removing the E from all the documentation. GECOS became GCOS, GEMAP -> GMAP etc...

AIUI Honeywell started it and partnered with Bull during the process.

True, AIR they made some of the processors for the DPS machines.

Reply to
Anthony Fremont

"Alan Balmer" wrote

You should see the looks I get when talking about "control cards" when referring to JCL. Every new programmer should have to punch up a deck and learn why sequence numbers are worth the effort. ;-)))

Reply to
Anthony Fremont

My error. I forgot to multiply by two cabinets D'oh!

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Guy Macon, Electronics Engineer & Project Manager for hire. 
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Guy Macon

Unless, of course, theres a glitch on the power rails or something that sends the PC off to neverland.

Assuming your hardware is perfect, which it's not.

Of course it can becom stuck. If the "clearWDT instruction becomes inaccessible" then something is very wrong. The watchdoing will timeout and reset the CPU. Thats the whole point!

If your 12c508 code is expected to be very reliable, then I'd include a watchdog.

Al

Reply to
Al Borowski

You guys are in the wrong place for this stuff. Try alt.folklore.computers. Crossposted and followups set. It is OT for comp.arch.embedded.

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fix (vb.): 1. to paper over, obscure, hide from public view; 2.
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Reply to
CBFalconer

IIRC, Univac 1108 was 36 bits / word.

Tauno Voipio tauno voipio @ iki fi

Reply to
Tauno Voipio

Are you sure about the 64 bit memory word length, since the 1108 was a

36 bit machine, so a 64 bit memory word width does not make sense even with parity or ECC bits. IIRC there was also some 1:1 interleave so that odd memory addresses came from one module and the even addresses from an other module, thus speeding up sequential access (a core memory read access required that the controller wrote back the value read back into the core).

Paul

Reply to
Paul Keinanen

Ah, thank you Anthony. In German we call it (translated) Ferrit Core Memory.

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42Bastian
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42Bastian Schick

Ha, now you got me why I could not come up with the right picture.

I thought core dump == kernel dump. But actually it's memory dump.

I loved this word, now I do like it even more :-)

Thanks.

BTW: I saw one, but only at the German Museum in Munich.

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42Bastian
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42Bastian Schick

It's comming around again : Ramtron's FerroElectric FRAMs also have a destructive read, and Motorola and Cypress are working on MRAM devices, but it's not clear if they have destructive reads. FRAMs do have a finite, but large, cycle count limit. Anyone know if the old CORE had the same wearout issues, or did they never cycle it long enough the those lower bus speeds to find out? :)

-jg

Reply to
Jim Granville

"Jim Granville" wrote

After a little googling it appears that they do and consequently have an automatic rewrite cycle generated internally. This is interesting in that you have to manage your read cycles as well as write cycle counts.

Reply to
Anthony Fremont

"Anthony Fremont" wrote in news:f0utc.14985$lY2.14045 @fe1.texas.rr.com:

/hug card sorter

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Richard
Reply to
Richard

Yes, that was a dumb of me to "derive". But it suggested this idea:-

You fill your MCU with NOPs plus one (RAM less) IO toggle and run it under EM and ES duress. If it latches permanently, you know the core is inherently vulnerable and you don't use that device.

We have to enable WDT to conform. I hate it because the only post production failure we had was WDT induced:

At cold temperatures the (CR) period of the (independent) WDT reduces by 20%. I did not realise this. I set all WDT reset-times at the most infrequent possible (at room temperature).

At low temperatures, our system became locked in a constant re-boot cycle.

Cheers Robin

Reply to
robin.pain

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