High Vin LDO with truely low dropout in small package (long post)

Thanks for the ideas.

Typically our devices have several power consumption levels. But I can't use multiple PS circuits for better efficiency because they don't make any that I have found that are efficient at low currents. The problem is not the dual mode, the problem is not the noise, the problem is that there are *NO* switching converter chips that meet all the requirements of input voltage, clock sync and good efficiency at low current. The high Vin chip market starts with parts that work at 1.5 amps and goes up from there.

A link to an article about using a capacitor as an intermediate power source:

"Supercapacitor boosts current from small battery"

- Tim

High frequency is the key. The high current spikes you mention are caused by the voltage differential combined with the low ESR of the caps. There is a peak of current at the onset of switching which ramps down as the voltages equalize. Then the current is strictly the load current which will ramp up the voltage on the high side cap(s) and ramp down the voltage on the output and low side caps.

By using a high frequency the initial delta V on the caps is smaller, reducing the spike current. The two phase circuit will also help, but it quickly becomes impractical for anything other than a 2:1 divider. To work well over a 7 to 17 volt input range, I am planning to implement 2:1, 3:1 and 4:1 voltage ratios and may even use 2.5:1 although that would just be icing on the cake to boost the efficiency over a fairly narrow range of Vin (8.5 to 10 volts).

I suppose that you could simply use a comparator and gate to halt the switcher---through a shudown input or by gating the clock.

This could all be moot if you are constrained on size---you will probably need a pretty large capacitor. However the super caps are getting better all the time.

Mark Borgerson

I'm not sure how this would be a better approach to this problem. It seems to be pushing the limits of what you can do with a switcher. I can't recall the startup times for switchers, but this sounds to me like it could be a very tricky circuit to get to work correctly over all conditions, especially when you add in something like a super cap that has very limited temperature range.

I think the point is moot now. The last thing I needed to check to see if it was viable was the drive for the PFETs. When I calulated the drive current required, I have a choice of switching them fast, or switching them with low current, I can't do both. I did not know that discrete FETs were so limited for speed. The part I had selected has an input capacitance of 600 pF!

This type of circuit might be practical inside a chip, but using discrete components makes it slow and unwieldy.

FAB capacity has been brokered for some time, now, and the pricing isn't scary. And also offered to universities at still lower prices. You might be able to get a decent number of your chips made at fairly okay costs and then shop them around. Just a thought.

Jon

Rick,

Will this work for you? :

I'm using the AIM-3.3V of this part in a design and it sounds like it's almost a perfect fit. Perhaps parallel two of them or use an external FET to get the 100 mA continuous.

John.

and this one looks a very good reality-check for any alternative discrete designs [4-40V ip] :

Still new, claims just 680uA for no load inductor mode, and it can select LDO mode, for ~40uA Iq (100mA pk). Has Reset and Sync to top off the features....

I see it also has a snap-action on rising Vin, which is something very few regulators do - benefit it is avoids brownout areas, and many devices have poor brownout behaviour.

-jg

Thanks for the pointer. It would have been perfect, but the sync is only good up to 500 kHz and we need 600 kHz. But this is exactly the type of part I would like to have.

Sync it to 600khz/2!

Interleaving two, out of phase, to get your 600KHz.

Efficiency vs: Load Current graph in the bottom right corner of pg. 6 shows only ~50% efficiency @ 10 mA, rising to 75% @ 14V input and

James Arthur

Yes, something seems not consistent in their data. They state 14Vin 5V out, Io=0, typ 680uA (9.52mW) But then show 62% on the graph for 14V/5V/10mA, [50mW], which suggests 30.6mW of losses. (2.2mA?)

Pity they don't plot Iq vs Io for BUCK mode.

-jg

That is a little puzzling, until you notice the buck mode Iq (they call it Is) spec at the top of pg.3 shows 720uA typ. for the 330KHz version,

Regardless, efficiency-wise it beats an LDO by quite a bit, and for all inputs.

Best, James Arthur

I've found a SMPS data sheet where they DO plot Iq vs Io, ( for a LTC3835 ), and that does show a variation in loss, under 10mA.

On this device the losses corner is appx 0.5mA : below that, the loss is effectively independant of Io, and above that, losses climb with io.

-so the maxim device might take 680uA at 0mA, and 2.2mA at 10mA Io.

Silly NOT to carry the graphs below 10mA, as someone might think they have more wastage than they really do.

-jg

so don't use them at low currents. only enable them when you need high current.

Bye. Jasen