Help with the TSB12LV32 1394 Link Controller

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Hi all,

I have designed a 4 layer board that has :

- TI TSB12LV32 1394 Link controller
- TI TSB41BA3 PHY device.
- Dual SVGA controllers.
- 2MW Fast SRAM.

The board has been designed to (initially) plug into a 5510 SD DSP
SDK. Ultimately the board will plug into a DSP board of our design.

The 1394 Link controller, SVGA controllers and Memory are all memory
mapped into the CE2,3 space of the DSP. The SVGA controllers and
Memory work without fault (ie. address/data bus and decoding looks

The problem I have is that the '32 is behaving erratically. A small
program has been created to continually display the '32's version
registers, which at first are indeed correct. After a small and
apparent random amount of time (generally less than 100 accesses but
occasionally up to 1000) the '32 appears to 'lock' up with the
following signal states scoped:

- nCS (pin7) falling low on each memory access as expected.  
- nTEA (pin3) continuously low.
- nMCA (pin 4) continuously low.
- nINT(pin1) continuously low
- nMWR(pin 8) high (read operation)
- nRES (pin 9) high (reset occurs at program start, a low for 500mS)
- BCLK (pin 6) 50MHz clock.
- COLDF (pin12) low
- SZ0 (pin 13) low
- SZ1 (pin 14) high
- Address bus correct

Note that the micro-controller interface (to the DSP) has been set for
16 bit handshaking mode. The logic that generates the 'ready' to the
DSP has been checked using an oscilloscope and appears to be correct
in that the DSP does indeed see the '32 indicate that the DSP  bus
cycle is complete, to which the DSP responds by releasing the CS(when
the '32 is responding that is). Note that on failure, the logic is
such that the cycle is terminated and the DSP continues, hence the
continuing CS's

Additionally, the '32 is powered from a separate 3.3V regulator (no

Finally, I did get caught out with the msb notation on the controller
(address and data bus) but this I doth think is a problem as the
device driver translates OK.

Any suggestions to chase prototype hardware faults, bus cycle setups
or are there any funnies with the LLC that I need to be aware of.

Any advice welcomed

Garry Jackson

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