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Re: Hands on PCI interface ...

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I was involved in chipset testing.  One of the prominent examples where ISA
transactions simply cannot be translated to properly formed PCI transactions is
in the case of ISA DMA.  There is no correct mapping possible -- the timing
requirements on the ISA side are "hard" and the PCI bus doesn't have the needed
transaction types to fully support ISA-side DMA without the sideband.  So the
Intel chipsets all (up to the point where I stopped working with them directly,
anyway) included pins which were simply called "sideband."  These pins couple
the southbridge with the main chipset in order to inform it about things like
ISA DMA, which have to be handled through PCI transactions but where the timing
requirements are hard and the chipset needs to support them.  This was necessary
as PCI transactions had to be "twisted" a bit to make this work.

This is what I mean by sideband -- these out-of-band communications between the
southbridge and the main chipset for support of things like ISA DMA timing.

It was these sideband channels that accounted for about 1/2 of all chipset bugs,
so I know these sidebands exist.  Plus, of course, I had to read the data sheets
and understand things like the inbound and outbound queuing, read around writes,
and a host of things regarding testing the chipsets with FPGA boards on both
sides of the southbridge, trying to break it.

Like I said, things may have changed.  It's possible that I'd barely recognize
the PCI, today (though I doubt things have changed that much.)  But I don't yet
see how ISA DMA timing, for one example, can be maintained exclusively through
standard PCI transactions and without any "extra communication" to the chipset.

I'm not saying that a reduced ISA wouldn't work -- it would.  But there are a
few bits of non-overlapping semantics between ISA and PCI.  And these are
usually handled by the sideband channel.  I can assure you that if Intel could
have gotten rid of it, they would have clawed and screamed to do so.  It was a
sink of engineering labor they would have been glad to be rid of.


Re: Hands on PCI interface ...

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The problem is a direct result of ordering rules. PCI (and basically all IO
buses) rely on certain ordering rules. Specific rules that apply in this
case are:

strong write ordering
- posted writes must arrive in order
- reads must flush writes (a read request must push posted writes ahead of
it (towards the target being read), and read completion (i.e. the read data)
must push posted writes ahead of it (toward the requestor of the read data)

deadlock avoidance
- writes must be able to pass requests (for example, read requests)

PCI has a retry mechanism for transactions and ISA does not. Once an ISA
device initiates a transaction there is no mechanism to get the master to
realease the bus until the transaction completes. The master can be held it
wait states, but you can't tell it to retry.

So, take the following scenario...

- the host has a posted write transaction heading towards the ISA bus (i.e.
it is temporarily stored in the chipset because the PCI bus was busy)

- the ISA bus is granted to a bus mastering device and the device intiates a
read of host memory

Without sideband signals, you have a deadlock condition. The read data being
returned the ISA bus master cannot be returned to the ISA bus before the
posted write that were buffered in the chipset. But, the posted write cannot
be delivered to the ISA bus because it is busy (the master is being held in
wait states waiting for the read data to be returned).

The sideband signals are used to make sure that the posted write buffers in
the chipset are flushed (empty) before an ISA bus master is granted the bus.

So, if you are implementing an ISA target device this isn't a problem (you
don't have an ISA bus master device).

These "sideband" signals are not documented in the PCI specifications. They
are chipset implementation specific signals and are private to the



Re: Hands on PCI interface ...

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I think it is possible if the ISA card can use 1 interrupt or share
interrupts. You'll need some intelligence to convert ISA DMA to PCI
bus mastering (which is more or less the same, only the addresses are
generated at a different spot). The amount of I/O and memory addresses
can be preset on the PCI card so substractive addressing isn't needed.

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Re: Hands on PCI interface ...

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The problem isn't that, it's the timing requirements of ISA DMA.  They simply
cannot be met by the PCI bus using normal PCI transactions.  This is part of why
the sideband signals are required to the main chipset, so that the chipset can
be informed about the non-standard nature of certain transactions.  Without
them, the DMA timing itself cannot be supported on the PCI.

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I suppose that's possible, of course.  Usually, ISA bus transactions are handled
as subtractive decoding, though.


Re: Hands on PCI interface ...

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I'm convinced it can be done with a trick: have the PCI-ISA bridge
read data from the ISA card first, store this and then send it to the
main memory. This way you separate the timing between the ISA and PCI
bus. This also allows for a smarter scheme in which more data is
buffered in the PCI bridge before it is send to the main memory.
You'll need to have the PCI bridge generate the addresses anyway.
Needless to say, you'll need to change the ISA driver software into a
PCI version as well.

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Re: Hands on PCI interface ...
snipped-for-privacy@gmail.com says...
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I've run across such things occasionally. Do a web search on '"PCI to
ISA" + card' or some such.  A quick search found these (rather
expensive) external chassis PCI to ISA extenders and I've seen others
(no idea how well any work):


PCI->ISA Bridge kits:



Re: Hands on PCI interface ...
How about this?

A modern PC motherboard with ISA slots?
I am looking for the fastest processor speed


Re: Hands on PCI interface ...

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How about this?


Re: Hands on PCI interface ...

I was asked to look for ISA MB with
decent speed by a co-worker.  I
had assumed he did a google
search and came up with nothing.

Thanks for the tip, and I will always
second-guess co-workers in the


Re: Hands on PCI interface ...

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Search for "passive backplane" in which case the CPU plug in card
contains most of the functionality these days.

Also some ITX size motherboards have PC/104 connectors, so I would not
be too surprised, if some even contained an ISA connector instead.

Re: Hands on PCI interface ...
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Re: Hands on PCI interface ...
<Nico> wrote:

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For the sake of argument...  ISA boards are still very available in the
industrial market, and I think will be for many years.  Cost is an issue
there, however.  Since you are looking to learn, it is a good entry level
bus.  Agreed, ISA is not exactly up to date technology.

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Nico, you didn't say what your price point is.

Someone else prove me wrong, but this is the lowest cost PCI proto board
I've seen.  $150 USD.  But wait -- there's more -- it includes USB, too.
It is CPLD based, so in theory you can use it for some other purposes
as well.... not as many options available as with a full FPGA, but a good
trade for the cost.


Thanks, Steve

Re: Hands on PCI interface ...
If anyone actually wants to play with ISA design, I have a 16 bit ISA proto card
gathering dust. It's a JDR Microdevices PDS-611:


All docs available, for sale for $41.44 (or half of whatever JDR wants that
day) plus shipping from New York.


Chris Candreva  -- snipped-for-privacy@westnet.com -- (914) 967-7816
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Re: Hands on PCI interface ...
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Like most other people, I'd recommend PLX, it's cheap enough especially
for simple targets (no bus mastering). You probably won't understand the
PCI bus much more after you've done it though- you are insulated from
all that if you just follow the reference design.

For drivers, TVicH co0mes to mind, it's shareware, so you get a bother
screen until you buy it, but it's reasonably cheap.

Paul Burke

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