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Generating 6MHz output frequency

I need to drive a 320x240x8bbp TFT color display (Hitachi XT14 series). I need to provide a clock signal @ ~6MHz and I can't use a micro with a built in controller.

Options are:

1) driving the TFT directly from the microcontroller 2) using an EPSON controller (or a dedicate FPGA)

As I have to use STR9 chip, I'm trying to figure out if I can really obtain this output frequency: the problem is that the micro PLL can raise the internal clock frequency upto 96MHz. At first look, I might have to invoke a sort of IRQ @ 12MHz to drive the output pin HIGH-LOW with 50% duty-cycle: may I use a timer output compare interrupt, but here comes the trouble.

12Mhz means Toutput = 83.3nsec 96Mhz means Tclock = 10.4nsec

So I have just 8 clock cycles between two consecutive IRQs. Considering that I have to get pixel value from DRAM, decode it to RGB palette and the put it on the output pins..... (not to speak about the needed IRQ control overhead).

This morning I've begun to look at EPSON / FPGA controller :P

Points are:

0) can STR9 pins be swapped HIGH to LOW at 6Mhz @96MHz clock? 1) is there any tricky solution? 2) Is there some VHDL code ready to drive a TFT display: I've got short time to market and I can't afford a FPGA development. 3) any other suggestion will be very appreciated

Thanks!

Reply to
djordj
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Hi, I'm most definitely NOT an expert (I'm still investigating driving an embedded LCD), but an FPGA looks like a great option to me. This guy's web site explains how to drive an LCD with an FPGA, and he provides sample code when you purchase his products.

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If you email him (check his contact page), he may even have some ready-made solutions for you.

Good luck!

Steve

Reply to
svrusso1

You do not want to do this in an IRQ. Where does the STR9 get the ref for the 96MHz PLL ? Commonly you would have a 6 or 12Mhz Xtal Osc module, and then PLL that up to the 96MHz, ie you just choose your initial XTAL so it is easy to get 6MHz from it.

If there are other complexities, I'd also look at a small CPLD, which can handle the MHz region clocks very easily, and re-frame the datastreams into something the uC can manage.

-jg

Reply to
Jim Granville

Jim Granville explained on 13/12/2006 :

I've been thinking this way too, but I'm having a 8MHz built on the board. Even if this clock would be nice, I still got the problem of data sync: in a simple way, I have to load something like a 32 bit value and output them before I latch the clock up. In fact, TFTs latch input bits on the rising edge of the main clock: how can I sync the internal data load procedure with an external clock signal driven to the uC and to the TFT?

Maybe it's another solution: do you have any link?

Thank you very much

Reply to
djordj

Depends very much on the bandwidths, DMA into a SSC on the devic is one way to stream data efficently. If that is not enough, then you'll need a more dedicated LCD controller.

Atmel ATF1502BE/ATF1504BE Altera MAX II etc Lattice MachXO etc Xilinx XC2Cxx etc Actel ProASIC

-jg

Reply to
Jim Granville

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