FPGA to ASIC + JTAG chain insertion

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Hi all,

We have to do a FPGA-to-ASIC conversion with JTAG chain insertion.

The design was tested on spartan-II and was converted to ATMEL MG2
successfully via Leonardo Spectrum (functional test and sdf timing).

Now we have to use MENTOR DFT Suite for the JTAG insertion and test
coverage.

The documentation from MENTOR is very complet, and/or maybe a bit too
complet.

My questions is:

Do you have any experience with the MENTOR DFT Suite.
Are there any application note, paper ... resuming experiences with this
design flow?

Thank you in advance,

Laurent Gauch
www.amontec.com

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