FPGA board - Avnet's $39 board?

Digilent has a few inexpensive FPGA boards. Once upon a time they also included a parallel JTAG cable with most of their boards but, with parallel ports disappearing, they've switched to including on-board USB-to-JTAG capability on the newer ones. If you have a real parallel port, they do sell JTAG-3 cables for about US$12.

This one offers an on-board VGA port as well as a fair amount of SDRAM, at pretty close to your price point.

Also look at

They have some interesting offerings as well.

Both Xilinx and Altera offer free downloadable versions of their tools.

--
Rich Webb     Norfolk, VA

Hmm! Digilent's products look to cover my app space better. I'm deciding if the BASYS is enough... I need to map out the requirements in a bit more detail.

Thanks for the pointers! Seems I do one of these projects only every couple of years, so I'm never up to speed with what's available.

Order it and wait - that's what I did. Even though it was "out of stock".

In 2~3 weeks it was dropped on my door step.

How did you order it? The price is $call and it can't be added to a cart!

For your needs, I highly recommend an older Digilent board, the S3 board, priced at $99 with power supply and download cable. The FPGA on the board is an XC3S1000, which has more than enough room for an 8051. Here's a link.

There was a prior thread on comp.arch.fpga titled, 'Nintendo DS Screenshots / Video Capture', from which I have copied my reasons for recommending the S3Board over the S3E board.

*** begin extracted text *** For a newbie such as yourself (or even an oldie like me) and a project such as this, I highly recommend the S3 kit over the S3E kit, for a number of reasons.

1. The expansion connectors on the S3 are standard 0.1 inch pitch headers, while the S3E board uses a Hirose fine pitch connector for most of the FPGA I/O. There are some 6-pin 0.1 inch connectors on the 3E board, but the total number of I/O available on these connectors is a small fraction of the FPGA I/O. It is much easier for a hobbyist (or even a professional) to connect stuff to the 0.1 inch headers.
2. The RAM on the S3 board is SRAM, while the S3E board only has DDR2 SDRAM. It is orders of magnitude easier to implement a frame buffer (which you will need for your project) in SRAM than DDR2 DRAM. The DDR2 requires a controller, while the POSR (Plain Old Static RAM) just requires you to hook up the address and data lines.
3. The LED display one the S3 board is very easy to use, while the LCD on the S3E requires more circuitry to initialize and send data to the display. The only thing you need for the LED display is some matrix scanning code, which is provided by Xilinx in their demo code (which is written in VHDL, not verilog). The LED display is very handy for debugging.
4. The S3 board has 8 slide switches and 4 pushbutton switches for general use, while the S3E board primarily uses a rotary encoder which needs to be decoded. Switches are also great for debugging and changing operating modes easily.

*** end extracted text ***

As you can see, the S3Board has externally connected, 256Kbyte x 32 bit,

10 ns, SRAM. There is plenty of bandwidth to easily implement a tiled (character-based) display system as well as provide code storage for a CPU. The 10ns random access time for this SRAM is much faster than the 70ns random access time of the cellular RAM used on the NEXSYS2 board.

The BASYS board has no externally connected SRAM, and the 100K gate FPGA would not be enough gates to include a CPU.

Interesting that you mentioned the 8051 as a processor to include in the FPGA. In fact, I found an 8052 on opencores.org that also has the 8K Intel BASIC-52 interpreter ROM code. I have targeted this to the NEXSYS board, using FPGA blockrams to implement the 8K ROMS to hold the BASIC and to also implement an additional 4K of RAM for BASIC programs and stack/variable space for the interpreter. Communication is through a serial line with autobaud implemented.

As a test, after reading your post I retargeted the 8052 with BASIC ROM

• 4K RAM to the XC2S200-FT256 FPGA used on the S3BOARD - and it fit! There are still 6 blockrams (out of 12 unused), but the logic is mostly full. However, the logic to implement a graphics tiling is almost nothing - mainly just concatenating some counters and character values to generate SRAM addresses. I suspect that the sprite processing hardware will fit also, unless it is really sophisticated.

I also have working VHDL code to implement a bitmapped XGA resolution (1024 x 768) display using the external SRAM. The input to the SRAM is via SPI, but could be easily replaced with code to map the frame memory into a portion of the 8051 address space. Note that bitmapped display doesn't have any arbitration code at this time - the non-display port has priority, which causes screen 'hash' when writing to the display. This would be easy to fix, though.

I'm going to try and add the XGA display controller code to the 8052 code and see if it still fits. I'll let you know how it turns out.

I have a long background with Xilinx FPGAs and several of their eval kits, as well as experience programming a tiled/sprite-based graphics system (PARSEC on the long-defunct TI 99/4A). If your effort is directed toward student learning, I would love to work with you on this project. If you are interested, send an email to moctodscinobrutabru (reverse this email address, replace the obligitary dot/at, and substitute an 'x' for the 'cs' at the end of the domain name.

I've written several tilemap & sprite-based modules and the resource requirements are trivial. On Altera the tilemap logic is 65 cells, whilst the sprite logic for 8 sprites is 29 cells.

Also, the original impetus for a tilemap/sprite system back in the day was the minimal RAM requirements - 1 or 2KB of memory is plenty for a usable display - and using internal dual-port RAM blocks is especially attractive in this case. Tile and sprite data can be stored in (external) single-port RAM where no arbitration is required.

Not having a go at you at all Paul, but I noticed... from

"This was the first game to use bit map graphics on the TI-99/4A, which is one of the reasons for the big leap in graphics quality over many earlier games."

So... tilemap/sprite system...??? :)

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Actually, Mark, the video chip used in the TI 99/4A, the TMS9918A, was fundamentally a tiled/sprite display controller. The 'bitmap II' mode that was used in Parsec was modified tiled display modes whereby there were 3 different character set definitions for the upper, middle, and lower thirds of the screen. And some of the elements for Parsec, such as the scorekeeping, used the tiled (character) aspect of the display where the character definitions were not changed. All of the movable objects, such as player ship, enemy ships, and asteroids, were sprites.

Now, you didn't make your post to sprite me, did you? :)

Perhaps they've sold out the next shipment already? Give them a call to see what's up.

d17e5b36c12643e0#

I have two of these boards. Avnet changes the website to prevent orders when they run out of boards. These boards turned out to be much more popular than Avnet expected. The FPGA on it is quite capable. I put an 8 voice polyphonic MIDI music synthesizer in one.

That was a fu-tile attempt at humour Paul! :P

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266