FIFO with 8 bit input, 32 bit output?

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I need a FIFO, with an 8 bit input, and a 32 bit output (one output
is read for every four inputs).  The inputs will arrive at 25 MHz.
The input and output clocks are asynchronous.  I would like it at
least 256 bytes deep, but more is better.

A co-worker suggested that I just line up four 8-bit FIFOs and
multiplex the input clocks.  But I would rather have a one-chip
solution, rather than 4 FIFO chips plus the multiplexer circuit.

Another co-worker suggested an FPGA, but I have never done that
before (although I have played around with a Verilog simulator),
and don't know if it can be done cheap enough (I would like to
keep the cost under $10).  Besides, I have heard that FPGA's are
current hogs.

If anyone has any good ideas, please let me know.

   -bob

Re: FIFO with 8 bit input, 32 bit output?
Bob schrieb:

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The other way round would be more effective: one 8-bit FIFO, and
decoding/demultiplexing at its output to get 32-bit words.
What's the maximum output rate?

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Memory capacity will always be a problem with programmable logic.
You end up with a *very* large device just to get all those flipflops
required for the FIFO.

Eventually it could be done with a CPLD and a dual-ported memory.
It might also be possible with a standard RAM, if you buffer the
input data within the CPLD and write it to the RAM between the
output accesses. (Will become a rather complex timing, however.)

Modern (and rather small) 3.3V CPLDs don't consume too much power, BTW.

--
Dipl.-Ing. Tilmann Reh
Autometer GmbH Siegen - Elektronik nach Maß.
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Re: FIFO with 8 bit input, 32 bit output?

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You wouldn't implement the memory in flip-flops -- any FPGA you'd
consider using will have enough RAM blocks to do the job.

-a

Re: FIFO with 8 bit input, 32 bit output?
: I need a FIFO, with an 8 bit input, and a 32 bit output (one output
: is read for every four inputs).  The inputs will arrive at 25 MHz.
: The input and output clocks are asynchronous.  I would like it at
: least 256 bytes deep, but more is better.

In IDT terminology, this is called "bus-matching."
Have you done even a preliminary product search?

 http://www1.idt.com/pcms/getDoc.taf?docID10%130
 http://www.idt.com/products/docs/FIFO_Selector%20Guide20030604.pdf

But there is a catch - these devices are highly expensive and
an overkill to most applications. Usually a few 74HC7030
'9bit x 64word FIFO' plus glue will suffice.

--
  ******************************************************
  Never ever underestimate the power of human stupidity.
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Re: FIFO with 8 bit input, 32 bit output?
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I think FPGAs are the way to go.
There are two possible architectures.
Clock FPGA at 25 MHz
    Need to use dual port RAM.
Clock FPGA at 50 MHz +    which gives higher power consumption.
    You can then use a single port memory which is
    written by the input block and read by the output block.


The AT94S05/10/40 are single package solutions (include configurators)
which contains a number of 32 x 4 Dual port RAM and up
to 16 kB of single port 8 bit RAM.
(It contains an AVR micro as well)
The part is limited to 25 MHz today, but this limitation
is for the AVR part, and you can run the FPGA faster.
The new AX series will run the AVR at 40 Mhz.

2 x DPRAMs make one 32 x 8 DPRAMs.
16 x DPRAMs make one 256 x 8 FIFO and you need 4.
This means that the AT94S40 is needed, otherwise you dont get enough DPRAMs.


You can also use the 16 kB x 8 single port RAM if you run that at 50 MHz.
Then you store everything in the RAM, but read out
to a single 32 x 32 FIFO built out of 8 DPRAM blocks
In this case you can use the smallest part.
Current parts might be on the border for speed, so
I think you probably want to go for the AT94S10AX to get the speed.

--
Best Regard
Ulf Samuelsson



Re: FIFO with 8 bit input, 32 bit output?
Use a small FPGA.  

The smallest available from Xilinx or Altera will do for your
application.  You can easily find one under $10, I suggest a Xilinx
XC2S15 in a 100 pin VQFP.  It's small, cheap and has enough
performance and capacity to handle your design.  This part can build a
512x32 fifo.

The HDL design is relatively straightforward and the vendor's free
"webpack" tools are sufficient to build it.

You didn't mention anything about volume or product life.  I suggested
that part since it meets your needs today.  If you decide to go this
way, you probably want to talk with a Xilinx distributor/AE about
whether it's appropriate for your product life time.

Chris


snipped-for-privacy@slackware.com (Bob) wrote in message
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Re: FIFO with 8 bit input, 32 bit output?

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For a radical idea, how about using a 160Mhz Ubicom ip2k single chip
micro?

Dedicate 4 8 bit ports for the output 32 bits, one 8 bit port for the
input and another for the handshaking. If your data arrives at a
constant 25Mhz, it might be a little tight, 6 instructions per input
byte.... If your data is bursty with some known gaps, it might be
doable. Also there is some automatic handshaking built in for printer
like ports that might help. Has about 4k bytes of plain ram built in
for a fifo. If the data was slower there also is around 16k bytes of
program ram, part of which you could use a fifo.

If you have any quantity say 10k plus it would fit your price point.
To prototype see http://www.ultradense.com /. I am not affiliated with
ultradense and do not know how good they are at support.



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