John,
I might have missed something, but if you need a FIFO size of 8K x 48Bits you'll get that into most reasonable sixed FPGAs these days (Cyclones or Spartans). Otherwise hang a DRAM off it as rickman says.
If your data rate to the FPGA is only 1MByte/second you could almost get away with one of the FTDI USB 1.1 interfaces (FT245R gives an 8 bit fifo output).
If this isn't sufficient there are a couple of easy to implement microcontrollers about that give you a FIFO interface at USB 2.0 full speed data rates.
The host PC would need to do more of the work but if this is acceptable then an embedded SBC seems like complete overkill?
Nial.