Hi,
I'm working on a proposal to design a box that will control a scientific gadget. Our box will output frequency sweeps, arbitrary waveforms, a couple of dozen voltages that can be changed/ramped per user desires, and some discrete logic levels and triggers.
One architecture would pack an Intel-cpu SBC and a custom board in a
2U rack box. The SBC would talk gigabit ethernet to the customer's system and PCI to our board.Something like this, maybe:
Our board would have a PCI interface driving a biggish FIFO, say 8k deep by 48 bits wide, inside an FPGA. A simple state machine/latch/mux thing repacks the 32-bit pci transfers into the input of the 48-bit wide fifo. The output side of the FIFO would be driving a fairly simple state machine; each fifo word has an opcode field and a data field, with different opcodes feeding various devices connected to the physics... dds synthesizers, ttl outputs, whatever. The state machine that unloads the fifo would run at 128 MHz, but one opcode is WAIT, so we can slow down operations to match the realtime needs of the experiment and reduce the average fifo feed rate.
OK, we finally get to a question: If we run some flavor of Linux on the SBC, what's a good strategy for keeping the fifo loaded? Assuming that we have the recipe for an entire experimental shot in program ram, some tens of megabytes maybe, we could...
- Have the fifo logic interrupt the cpu when the fifo is, say, half empty. The isr would compute how empty the fifo actually is at that instant and set up a short dma transfer to top it off.
- A task (or isr) would be run periodically, a thousand times per second might work, and it would be responsible for topping off the fifo, either dma or maybe just poking in the data in a loop.
- Best, if possible: set up a single DMA transfer to do the entire shot. That involves a dma controller that understands that the target is sometimes busy, and retries after getting bounced. I know the pci bus has hooks for split transfers, but I don't know if standard Intel-type dma controllers can work in this mode.
- If it's a dual-core cpu, is it hard (under Linux) to assign one cpu to just do the fifo transfers?
- Other ideas?
The problem is not unlike feeding a sound card. How does that work? Maybe we could start with a sound card driver and hack that?
Any suggestions for resources? Books, model drivers, references, people we could hire to write the drivers for us? Being a hardware guy, mostly analog at that, I don't know much about this stuff.
Right now, I only have to write up a plausible proposed architecture, but if we get the job, p>=0.5 maybe, we'll have to do actually it.
Thanks!
John