Dear Ulf @ All,
I reviewed several low power wireless chipsets from different vendors. They typically drain about 20mA @ 3.3V when in the active Rx or Tx mode, and less then 1mA in sleep. Switching from sleep to active incurs the overhead of several milliseconds; unfortunately none of the transceivers retain the bit synchronization between the packets; there is no easy way to synchronize the nodes to the master to a fraction of the bit interval. As noted by David and Mark, it could be possible to fit the
10mW constraint if the system cycle time is several seconds; but it is hardly feasible with the cycle time < 1 sec.Next question: are there any off-the-shelf wireless modules that could allow for the ~1/100 duty cycle operation with ~10ms packets with the average power consumption ~10mW ?
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant