Experience with AD5328 DAC

Yes, similar and without problems. It's hard to give more help than that with what little information you have provided. Sorry.

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Dan Henry

As mentioned in the datasheet, I've implemented in software SPI protocol with CPOL=0, CPHA=1 (clock active low, shift data out on the falling SCLK edge). The problem is that on DAC update only channel A is updated and only values 2^n-1 (1, 3,..., 127,...1023, 2047, 4095) are accepted. Even commands (like 'reset') are not executed. I even tried different versions of the protocol (allways shifting on falling SCLK edge) but without any success. LDAC pin is permanently tied low.

Datasheet mentions (in timing diagram) that all values are specified with tr=tf=5ns. I don't know if this is the constraint, as in my case rise and fall times are more than 50 ns.

DAC behaviour is really strange... and I'm out of ideas what may me wrong.

Damir

Perhaps a framing problem -- what about the SYNC signal?

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Dan Henry

Also, I'd shift data out of the master on the rising edge so the data is ready for the slave (DAC) to shift in on the falling edge.

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Dan Henry

I haven't used the AD part but I am working with a similar one from TI, the TLV5628.

It's almost impossible to troubleshoot SPI without looking at the actual timing. Any chance that you could grab a screen shot and post it to alt.binaries.schematics.electronic?

You can use a two channel scope if you really have to, by walking up and down the signals pair-wise, but a logic analyzer makes it much, much easier.

The Ant8 or Ant16 from Rocky Logic

[1] aren't too expensive and either would do the trick. I used an Ant8 from right when they became available as a portable, stick-it-in-the-laptop-bag tester. Recently sold it and got a LogicPort device that I've been very happy with: Very rarely ever use the boat anchor "real" logic analyzer in the lab any more.

[1] Their server is reporting 403 Forbidden today. Don't know what's up with that.

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Rich Webb   Norfolk, VA

Sync is stable low before first clock high-to-low transition, and goes high after last clock.

I shift out (change) data while SCLK is high and data is stable for 500 ns before SCLK falling edge - I will try to change protocol and change data on the SDA line at the SCLK rising edge - but I doubt that this will make any change.

I will also try to capture screens from the scope and post images on the binaries group.

Thanks for help - to you and Rich!

Damir

Please post here saying that you did. Of my two Usenet access means, one does not allow access to the alt.* groups. I would like to know if/when to look for scope captures.

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Dan Henry