Embedded software interview question collection

Pretty please don't top-post.

Interesting compiler treatment of volatile by the compiler.

IOW, your seeing the cached value of the memory location (which isn't memory).

What are the other variables on the cache line? More registers? RAM? If registers, then you need to disable the cache for that region of memory. It would be highly unlikely that the locations surrounding a status register would be RAM used for "normal" program variables.

--
Michael N. Moran           (h) 770 516 7918
5009 Old Field Ct.         (c) 678 521 5460
 Click to see the full signature
Reply to
Michael N. Moran
Loading thread data ...

Actually I use it fairly frequently for readonly status registers. It's good code hygiene.

Robert

Reply to
Robert Adsett

I can't recall any situations where I had such problems. But I certainly know what problems can occur, and ways to remedy them. The project I'm working on now had the problem before I joined the company. I've probably worked on other systems systems that had priority inversion going on somewhere, but which didn't cause bugs that were noticed or important enough to fix right away. (usually only a portion of real-time code actually has timing requirements)

A much more commonly encountered bug though would be deadlock. I've run across several candidates that don't do well even describing what this is in the general case and draw a complicated diagram on the whiteboard trying to explain them. (worse is when I find this bug in a commercial RTOS component and their developer working on the fix doesn't seem to understand deadlocks)

-- Darin Johnson

Reply to
Darin Johnson

I suppose the sequence may depend on the attractiveness and responsibility of the candidate. Can't get a girl until he has a house and then, once he has one whoops here come kids - better make her a wife ;-)

I think the need for extra-curricular activity decreases as you get older but if I was recruiting fresh graduates then I would be very keen to find out what they have done over and above their schooling.

Reply to
Tom Lucas

And then tell him which processor he has to use because the manufacturer gave the procurement department a particularly fine lunch and became the preferred supplier :-p

Reply to
Tom Lucas

I agree. I'd ask the question mainly to see whether I got a baffled expression or some kind of cogent response, whether or not they'd actually had the face the problem. It's just always better to say "tell me about a case where you had to ..." than to say "tell me in what situation this might happen and how you would handle it". IOW, ask for actual experiences, not taught techniques.

Reply to
Clifford Heath

In embedded programming, the biggest use of non-cache access (and of volatile access) is for accessing memory mapped peripherals.

Sometimes it is possible for the processor to choose to avoid the cache

- the Nios soft processor from Altera uses the highest address bit to indicate a non-cache access, and thus "volatile" avoids the cache. However, that's an unusual case. The most common volatile/cache problem is the misunderstanding that some people have when they believe that "volatile" accesses avoid the cache.

Reply to
David Brown

True, and this could be catagorized as DMA. The peripheral directly modifies the memory mapped registers.

I was not aware of such a processor. My only hands-on experience with caches is on the AT91RM9200 (ARM 920T). On this one you can tell the MMU which areas to cache and which not. As I understand it, this is far more common the your Nios example. Volatile has no effect on the cache, but is needed in addition to turning the cache off for the I/O areas.

Also got bitten by the cache when using a serial driver that uses the PDC (sort of DMA on AT91 devices). I had to use an uncached area of memory for the PDC buffers to get it working.

--
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)
Reply to
Stef

That strikes me as a strange way to view it, but I suppose it depends on where you are coming from - for my type of programming, caches and DMA are very high-end features, while memory-mapped peripherals are accessed continuously.

That's a much more common arrangement (and you can configure cache areas on the Nios too) - I was just using it as an example.

Yes, DMA and caches are fun. Live is a lot easier when your cpu clock speeds match your memory speeds and you don't have to bother with caches.

Reply to
David Brown

There are quite a lot of people who do not lock multiple resources or design their data structures in such a way that atomic variable updates can be used or use the RTOS in a way that each data structure has a clear owner.

I first heard the term "priority inversion" when NASA had some problems with their Mars rovers perhaps a decade ago, but I had not encountered that problem previously, even after working with various real time kernels for more than a decade before that.

Paul

Reply to
Paul Keinanen

Maybe a bit odd to look at it like that, but plausable. But I must admit I only thought of it to get out of the fact that I had overlooked the most obvious reason for using volatile. ;-) Sorry about that.

--
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)
Reply to
Stef

A proud personal achievement of my own was when I turned a $10K+ logic analyzer into a $25 voltmeter.

I just twiddled with the switching thresholds of several inputs, then hooked them on the same line...

Not so instant A/D converter.

Although this is very useful when a signal is expected to stay within a range.

Rufus

Reply to
Rufus V. Smith

Reminds me of a time I showed an acquaintance the limits of a logic analyzer - it doesn't tell you what voltages or ringing occured. All it does is show a threshold was crossed. I did some work with the menus in a HP (now Agilent) analyzer to trigger a LeCroy scope to nail down a problem.

Cheers

PeteS

Reply to
PeteS

I think, this guy himself is preparing for the interviews questions t face.

it's

at

could

trick

Reply to
badal_akr

Perhaps this is a test to see if the interviewee is alert enough to realize that the questions as presented are impossible to answer without further information. If that is the intent, it represents a common real-world situation...

Reply to
Everett M. Greene

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.