Hello We are working on intrinsic evolution wherein we try to evolve large digital circuits using PDCGP algorithm, using techniques which include partitioning, compaction,etc. Actually we have a timeframe constraint of about 3 months for the project. So wondering if generation of EDIF from C is possible within that timeframe, considering that this is just a module in the whole project. Would it be a better idea to pass parameters from C and use JHDL
formatting link
to generate the netlist directly? Can JHDL code be made generic for all kinds of circuits? Regards Quad