Eagle CAD and 672 pin TBGA ?

Hi Group

Did anyone managed to create a desing with such a high pin count device like the one mentioned in the subject using Eagle Cad?

I already use Eagle 4.0 but I figure would have to upgrade to 4.1 in order to have support for blind vias. Should I do this or better avoid investing more money into Eagle and choose another CAD package? If so, which one would the group recomend for this kind of tasks?

TIA

Markus

Reply to
Markus Zingg
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I'm working on a design with 1.27mm 272-ball TEBGA right now. Actually I've done the fanout from the part already and I'm working on some other parts of the board.

I believe there is no money investment, EAGLE license is valid for all major versions, i.e. your 4.0 license should be good up to 4.99. I have a full license that was originally for 4.09 and I'm now running 4.15 on the same license.

Reply to
larwe

Hmmm - glad to hear this - however 672 pins is quite a bit more than yours. Do you think I will manage to create a symbol for the part that still fit's on the screen?

Unfortunately not. The licenses I got with 4.09something I does not run with 4.15. Well, I don't mind to pay the fee (~200 euros if I remember correctly) if it's doable. I just don't want to spend it to later on see that I have to trash Eagle and use something differrent.

Markus

Reply to
Markus Zingg

Not unless you zoom out REALLY far :) So you use multiple gates. I split my micro into three gates - power, clock and "the rest". "The rest" is a very big symbol indeed, I should have probably split the PCI signals off onto a separate symbol. Another approach is to eschew the standard hairy rectangle style and instead just have rows of pins next to each other, much more compact onscreen. I don't like that very much.

(Actually I put my library up for download on Cadsoft's site, search for MPC5200).

That's weird, I would check with Cadsoft support on this issue. I am sure I read an explicit statement to that effect.

Reply to
larwe

Hello larwe, Markus,

I would suggest a multi-gate symbol for such a large device. I've done up to a 476-pin FPGA in Eagle and there is no reason why you can't go higher. But I think you will want smaller symbol chunks to be useable.

To place different "gates" as eagle calls them (really just one of multiple symbols used in a device) use the invoke command. It will show you which symbols need to be placed and which have already been placed.

I have a BASH script that is going to be part of a tool set I'll be releasing for Eagle (sort of a power tools-like offering) that will generate an Eagle script that will create your FPGA footprint in about

10 seconds or less. Perhaps you'd like to be a beta-tester?

You will need a new license upgrade to get to 4.1 from 4.09. CadSoft has a bit different view on version numbers than most other software companies. But the good thing is that you only have to pay incremental prices and not the whole price again.

You'll have to check the list of fixes to see if there is anything you need. 4.09 might be OK for you.

James.

Reply to
James Morrison

Do you think I could get away with the fan out without using blind vias?

If it saves me time - of course! My reply e-mail address is valid / working.

As I can see now, only blind vias would be missing but provided I will not end up being traped in a dead end with eagly, I'm fine with upgrading. If they only could implement some kind of online upgrade option. Sending in the license certificate and then waiting for the upgrade to arrive by snail mail is really not so cool.

Thanks for your reply. This helps a lot.

Markus

Reply to
Markus Zingg

:)))

OK, you piqued my curiosity so I dug out all my CDs and paperwork and discovered that we originally bought 4.09 for Windows only. Some time later we upgraded to a cross-platform Win/Linux license. When we did so, 4.11 was the current version, so the new keydisk had a 4.1x key. That's the one I'm using with 4.15 right now.

Reply to
larwe

You can do it if you have enough layers. I don't know the device you are using. Typically there will be a bunch of inner pins that will all be power or ground. These just need to go to vias obviously.

You will need (n-1) layers where n is the number of I/O rows. This assumes that the middle all ground and power and the outside rows are all I/O. Basically you can access the top two rows with the top layer (no vias required) and then you'll need one layer for each additional row. If you don't use every I/O pin you may be able to optimise.

FPGA's have the added benefit that you can pick your pinout as well to reduce vias. Vias take lots of space.

I posted a pretty extensive suggestion on routing BGA's with eagle on one of the CadSoft forums in response a posting from larwe (small world!). Check it out as it has a few lessons I learned that you might be able to avoid.

I'll email it to you, let me know what you think.

Agreed. You can download the latest version from the web so all you need is the license disk and code. They should be able to email the code and disk contents to you if you're in a big hurry. But if you aren't going to use blind/buried vias than you can upgrade at any time really.

James.

Reply to
James Morrison
[very informative post snipped due to limits imposed by my newsserver]

Unfortunately they don't do this. Remember - they are Germans :-( The only option to speed things up is to physically visit them. No option for me cause way to far away.

Thanks for above info. I defniately will scan the CadSoft forum and eagerly await your mail.

Markus

Reply to
Markus Zingg

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