DMA typical times

Roughly clock times buswidth, so at 32bits and 100MHz, that'd be

Rene

Ergh, that is leaving out too many important details. RAM bandwidth is often the limiting factor. So it depends on the source/target of the DMA operation, and what clock options are set for that memory. Also depends on what the priority is between CPU and DMA, the CPU's cache capabilities, and what the code is doing.

Essentially there is no generic answer to the OP's question.

Sorry to not point out. My number can be considered upper limit. RAM is a bit faster. DDR RAM get data on the falling and on the rising edge. That'd be 800MBytes then as upper limit.

Usually peripherals, except the tuned lot (LAN, Graphics, Disk) do not interface as 32bit.

Rene

To give an answer as specific as the OPs question...

The DMA burst transaction time of an embedded systems is usually equal to or greater than the memory subsystem minimum cycle time.

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For more details, lean about the ARM processors you need to simulate.

Study what DMA features are implemented in each variety of processor you are interested in.

Create the code required to initialize the DMA controller and respond to requests for data blocks.

Study the trade offs between the type of memory subsystem (SRAM, DRAM, DDRAM etc...), memory bus width and DMA burst transaction time to arrive at the total system estimated DMA through put.

Now evaluate all of this and create the simulation.

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Or ... Just build one and measure it.