DMA programming

The mode that you are talking about is entirely from DMAC / processor relationship dependent. Hidden DMA transfer means the DMAC will scan the execution of the processor and will find out when it is not using the data bus! and will utilize these clock cycles for data transfers. So processor is not slowed down and it continues normally. Obviously this data transfer should finish before memory access cycle of the processor. But there is a limitation that the processors which do have cache and pipeline should not use this mode. since they will prefetch the bytes from memory and will not wait till the execution state of the processor. Hence processors which do enable cache and use pipelining will not enable hidden DMA transfer mode of the DMAC. In this case they depend on the burst transfer mode of DMA which is quite common. Or sometimes cycle stealing mode also.

P4 use Cache and pipelining!

Cheers, Sagar

thnx! for ur reply .it quite cleared my doubt.....but i just wanna ask u smthing....... if i want to make both processor as well as DMA work simultaneously how it is possible. u can correct me if i m going wrong in my conception.thnx!

You can do it through hidden DMA transfer mode provided that processor doesn't use cache and it doesn't follow instrcution pipeline. Caches can be configured for write-through mode in whcih you can decide whether to avail the cache or not.This will always write into memory irrespective of cache. And you can disable the cache also. Also frankly speaking it should not happen. Consider an example of writing into same memory location by processor and the DMAC in vicinity of same clock cycles. Or one is writing and other is reading! If you are aware of burst transfer mode, DMAC raises HOLD signal and processor acknowledges by HLDA signal relinqishing the data bus and the DMAc does the burst transfer of data. So these are mutually exclusive processes.

Sagar

ya u r right that in burst transfer mode,DMAC raises HOLD signal and processor acknowledges by HLDA signal and relinquish the data bus.but as the data bus is under DMA control during this period processor cant be involved in transferring any data to external memory. can u please clear my one more doubt? i hav gone through hardware architecture of my OS.in that there is just an option for enabling DMA but if i want to do any programming for DMA how it can be accomplished? is there any procedure for this? thnx!

Let me make one thing clear . Changing modes of DMA is not a good practice and even general operating systems won't allow you to do that. Since if you change them, you have to handle lot many things... Like making the cache line invalid whenever the page is modified by DMA, keep track of updates of memory by application if they use write back mode before writing through DMA, and most importantly, the hardware should support all the three modes that we discusses in previous post. So most of the operating systems will take that care of programming DMA in appropriate mode (generally burst tranfer mode). Also there are several articles present on web for DMA programming. You can go through it.

Cheers, Sagar