Different stack pointers for different modes?

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Hi all,
Does anyone know if MIPS uses different stack pointers for different
operating modes, like ARM does?
Thanks.


Re: Different stack pointers for different modes?
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You wold not ask this question if you knew at least a little about MIPS.
First, MIPS has NO real stack pointer, so it cannot switch something it
doesn't have.

Read the 3rd volume of MIPS32 Architecture for Programmers, available
from www.mips.com for more info on operating modes etc.

BTW. Actually the architecture in its new version supports register
shadowing.

Re: Different stack pointers for different modes?
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Please understand that the ARM stack pointer in just a software
convention in native ARM (32 bit) mode. The Thumb instruction
set requires that r13 is used in push and pop instructions.

The ARM addressing requires that there is at least one register
free for storing the baseline registers when handling an interrupt.
Also, there has to be storage places for the baseline program
counter and status register. This is precisely what most ARM
exception modes do with banked SPSR, r13 and r14. FIQ is a bit
different, as there are more banked registers to enable exception
handling without any register save / restore.

In many RISC designs, there is no idea of a stack pointer
in hardware at all.

--

Tauno Voipio
tauno voipio (at) iki fi


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