Difference between Hardware and Software pll

Folks, We are in process to design a device with different sub- device, by sub-devices i mean with different clock requirements. The main processor we are considering to use comes with software configurable pll, that means you can actually classify the clock for fast, medium and slow devices. But there are some other cheap ICs out there doing the same job while multiplying/dividing the on-board clock frequency. I'll really appreciate is someone can clarify the following confusions:

0) What is the trade off between using software pll and hardware pll? 1) Say my main processor will be busy all the time while doing housekeeping; should i consider the hardware pll now? 2) Last but not least to metionn that all my sub-devices require very accurate clock.

regards, ali

Reply to
Ali
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What do you mean by software PLL? At normal clock rates, it doesn't normally make sense to implement a PLL with software. I assume you are asking about two different hardware implementations.

What are your specific frequency requirements? How does the processor clock multiplier fit with your requirements?

Sometimes you can get by with dividing down a high frequency signal, which might be done by a processor timer, but don't know if that works for you.

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Thad
Reply to
Thad Smith

For the OP:

What are your jitter requirements? All PLLs have jitter (it's guaranteed by the principle). You speak of a software PLL, but from context it seems you are speaking of software configurable PLLs. Is this correct?

Answer those and we might get somewhere.

Cheers

PeteS

Reply to
PeteS

Thanks Thad and PeteS for your responses. Snip from Thad:

By software PLL i meant a peripheral which comes right in my chip , for example TIs C55x series. And for the hardware i meant something like this [

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] CY22381.

I have a slow device of UART and DMA requirement with 50 MHz clock and my processor can actually make this happily. But, we think that having a separate and dedicated hardware might improve the performance, while reducing the burden form main processor. So what you say for that?

Snip form PeteS:

principle).

Well! i guess for slow devices its not an issue but for DMA we need accurate clock. As another device across the DMA will be having its own crystal of 50 MHz so synchronization will be the issue because of jitter.

cheers, ali

Reply to
Ali

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