Delayed Branching is a mechanism in which we asume that instructions that follow the instruction causing branch are useful and should NOT be preempted from pipeline. This results in reducing horizontal wastes. But the efficiency of technique highly relies over programmer and compiler.
My question is HOW TO IDENTIFY THAT NEXT INSTRUCTION IS DELAYED BRANCH ?
IF YOUR ANSWER IS "DECODE STEP" THEN I HAVE TWO QUESTIONS -
- DO WE HAVE ANY SUCH INSTRUCTION OR CLASS OF BRANCH INSTRUCTIONS THAT LEADS TO DELAYED BRANCHING ?
- WHAT ARE OTHER STEPS IN INSTRUCTION DECODING RELATED TO DELAYED BRANCH IDENTIFICATION ?
{What I know as of now is in this step we allocate physical registers for the logical registers in the given instruction. Such registers are kept busy untill instruction completes or(commits). Another thing that I know is CISC instruction decoding is quite complex as compared to RISC decoding because of its complex and variable length structure. CISC instruction needs an automata to decode an instruction as opposed to RISC where it is done in one step read.
Plz let me know if there are any other important things about Instruction Decoding.
}Regards, Ripunjay Tripathi