That is correct.
Got it. I was indeed assuming that time between write_to_sport() and state = TRANSMITTING was small enough to take allow the first transmission, but if something else delays the execution of the 'state = TRANSMITTING' instruction I may run in the race problem.
Indeed I think the hardware has a register to store the data and another to shift it out, hence as soon as the register is free to accept a new byte the interrupt will be asserted. This means that as soon as the first byte is written the interrupt is asserted (on next cycle), causing isr_sport() to run.
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uhm... interesting. I should maybe try to understand how the program sequencer works. [...]
indeed it is a memory mapped register defined as volatile and I declared it such since I thought this is the "way" to tell the compiler that the content of this variable may change due to hardware operations.
I was not aware that non volatile variables could be freely reordered. This will definitely screw up my logic, since I rely on things happening with certain chronological order (which is maybe a bad practice).
I understand, but I thought that having the isr_sport() only reading and the main() only writing I would have avoided this problem. Truth is that the first byte is read out by the main... ouch.