[cross-post] g21k and non-interruptible functions

I'm not sure exactly what David's referring to, but if you have a clock with a bit-count that's higher than the word width of your machine, and a clock read function that's guaranteed to take a small fraction of the time it takes for your clock to run through the bottom-most machine word of it's count, then you can make a dependable clock read that works in just three reads.

For example, if you have a 32 bit clock in a 16-bit machine, and it takes less than 32767 ticks to execute your function, you read the upper word, then the lower word, then the upper word. Like this:

upper_first_read = upper; lower_read = lower; upper_second_read = upper;

Then you look at the two upper word reads. If they're the same, then you construct your clock reading from a concatenation of either of them with the lower read. If they're different, then your look at the lower word: if it's less than 32768 you know that the clock rolled over between the first upper word read and the lower word read, so you concatenate the second upper and the lower word. If they're different and the lower word is large, you know that it rolled over _after_ the lower word was read, and you concatenate the lower word with the _first_ upper word.

I assume that this makes perfect sense to you now, and that you can see how, if the overall function doesn't get stalled for a good long time, that this is going to be dead reliable, forever. Or, you'll remember doing it.

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Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
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Tim Wescott
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I see. I thought may have been a problem in some manufacturer's mainstream MCU. in which case I wanted to know which one (in case I came across it :-)).

That may be true, but personally I would still not expect this behaviour when that specification is violated. I would have expected it to be treated as more like a spurious interrupt would be on a normal IRQ handler.

Although having said that, I can see how the internal MCU interrupt hardware logic, when it's triggered, might check FIQ to see if it's active, find out that it isn't and just wrongly assume it's been triggered as a result of a (now spurious) IRQ request.

I understand now. Thanks for having taken the time to explain.

Simon.

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Simon Clubley, clubley@remove_me.eisner.decus.org-Earth.UFP
Microsoft: Bringing you 1980s technology to a 21st century world
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Simon Clubley

an arm core is just a big chunk of logic, complying with specs like that needs to be done in the logic around it

yes, the irq and fiq inputs probably go straight to the sequencer it is not unlikely that it could get really confused if half the steps of handling the exception is done with the fiq asserted the other half not

snip

-Lasse

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langwadt

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