Confused with "task" keyword.

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I wrote a task to feed test vectors to my design, however, I realized some
differences between
"task" and the normal state machines I used to do. One sample code below, I
am expecting the
the signal "trd_sample" to be delayed by one cycle of "trc", i.e. 2nd
posedge of trc. However,
why does the simulation shows on the first posedge of trc?

I have put the modelsim waveform here.
http://img234.imageshack.us/img234/5034/confusedtask7bg.jpg

Thank you in advance.


module sim;
reg clk;
reg rst_n;

reg trw;
reg [3:0] trd;
reg trc;

reg [3:0] trd_sample;

always #5 clk <= ~ clk;

initial begin
 clk <= 1'b0;
 rst_n <= 1'b1;
 #1 rst_n <= 1'b0;
 #2 rst_n <= 1'b1;
 tx_in;
 $stop();
end



task tx_in;
integer i, j;
begin
 @ (posedge clk);
 @ (posedge clk);
 trc <= 1'b0;
 trw <= 1'b0;
 trd <= 4'h0;
 @ (posedge clk);
 trc <= 1'b1;
 trw <= 1'b1;
 trd <= 4'hA;
 @ (posedge clk);
 trc <= 1'b0;
 @ (posedge clk);
 trc <= 1'b1;
 trd <= 4'h9;
 @ (posedge clk);
 trc <= 1'b0;
 @ (posedge clk);
 trc <= 1'b1;
 trd <= 4'h8;
 @ (posedge clk);
 trc <= 1'b0;
 @ (posedge clk);
 trc <= 1'b1;
 trd <= 4'h7;
 @ (posedge clk);
 @ (posedge clk);
 @ (posedge clk);
 @ (posedge clk);
end
endtask

always @ (posedge trc or negedge rst_n) begin
if (~rst_n)
 trd_sample <= 4'h0;
else begin
 if (trw)
  trd_sample <= trd;
end
end

endmodule




Re: Confused with "task" keyword.

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Frank,
 I am confused as to what behavior you are expecting.  Your always@ block
 at the end will make trd_sample equal to trd every time that there is a
 posedge of trc.  Since you are using non-blocking assigments, the signals
 are assigned immediately, with no regards to clocks.  That also means
 that there is also no 'guarantee' of the order of assignment either. When
 you have three non-blocking assignments in sequence, the simulator might
 not execute them in the same order as written, generating some
 interesting race conditions.

Chuck

Re: Confused with "task" keyword.

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Thank you Chuck.
I am done by putting a unit delay at txd & trw, and I have better
understanding
over non/blocking assignment now.



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