CF Cards, status register, consequences of CORR bit?

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hi Group

The CompactFlash specification (section 6.1.5.9 in the CF2 specs)
denotes the CORR bit in the status register. Acording to the specs,
the bit is set "when a Correctable data error has been encountered and
the data has been corrected."

A subsequent write to a sector showing this behaviour make the bit go
off (seem to correct the "problem").

So far so good, but every now and then I encounter this condition in
the field with a smal percentage of installations. This rises the
following questions:

- Does this indicate a wear out of the card or is it just something
that might happen but otherwise can be ignored?

- What worries me is that if I place a card that showes this bit set
with a given sector in a PC CF card reader, the PC seem to look at
such sectors as bad and the read operation results in a read error.
However, as the specs state, if I read this sector with my embedded
system, the sector data is just fine.

- Does the fact that a subsequent write fixes the problem mean that
the flash memory area afected was hot swaped by the device?

- I use a FAT filesystem on the card, should I therefore copy the data
from the affected cluster to a new one and mark it bad (provied it's a
serious issue and the card does not swap it internally)?

- Does the ocurance of this mean a soon to be expected complete
failure of the card? That would be odd in that I also experienced this
with cards being virtually new...

TIA

Markus


Re: CF Cards, status register, consequences of CORR bit?
Ok group

It seems to be my destiny that whenever I ask a question here I end up
answering it by myself....

I contacted the supply channel of the CF's we use and got the reply
from their engineers which I embedd within my original text.

Quoted text here. Click to load it

--> It's not a WearOut, It just encounter an "ECC correctable error".
     Some NAND Flash block may happen this kind of error.
     It's not a bad block, just some bits defective (or charge lose).
     Controller have to correct it with ECC than reply host the
     corrected data.

Quoted text here. Click to load it

--> The returned data is no problem (correctable).
     Could you please get more Info about  "a given sector in a PC CF
     card reader"?
     Is this means "specific LBA"? with a specific CF_Reader?

(to answer this - yes and yes)

Quoted text here. Click to load it

--> Yes, we swap blocks for  "write operation".....IT's a kind of
     "WearLeveling". Basically, NAND blocks with "ECC correctable
      error" are not "bad blocks". They are not perfect but usable.
      We swap it for "WearLeveling" consideration, not for "ECC
      correctable error". That "ECC_Correctable" block may allocated
      to user disk area next time.....

Quoted text here. Click to load it

--> NO NEED. don't worry the data integrity.
     It's not a "wear out" condition, just the characteristic of NAND
     blocks.

Quoted text here. Click to load it
--> No. It's related to NAND block property, not NAND life time.
     We may say it's some kind of "Initial imperfect" of NAND
     block......Not perfect but usable.


Actually the answers reflect what I thought by myself already. I just
wanted to be sure. I hope this may help others if they stumble about
the same thing in the future.

Markus


Re: CF Cards, status register, consequences of CORR bit?
Quoted text here. Click to load it

Markus,

That happens to me to about half the time... but it's still worth asking.
Thanks for posting your findings.

By the way, the world's most complex interface for moving bytes from one
place to another place has just got more complex; the CompactFlash 3.0
specification has just been made available for download from
http://www.compactflash.org /. It adds Ultra DMA and new PIO modes 5 and 6 to
the TrueIDE mode and 80ns cycle times to the memory mode and 'advanced
PCMCIA IO' modes (the mode formely known as IO mode).


Tim



Site Timeline