I just don't use LDO where at all avoidable. And they usually are avoidable, meaning no tunnel of death :-)
LDOs have other pathologies which often aren't mentioned in the datasheet or possibly the chip guys didn't even know about them. My worst one was a LM29-something. Client insisted on keeping it against my advice. Phssst ... *BANG*. Hmm, we had babied the ESR so what the hell ...? Call into the mfg. The engineer there grew concerned and suggested a phone meet with the chip guys present. One could here some shuffling there in their room. More and more people came in, papers were perused, lots of mumbling in the background. Suddenly one guy let of an "Oh drat!" Turns out this LDO didn't "like it" if the source impedance got too high and we were feeding it from a week isolated path.
No imagine scenario #2: Joe Digital sees there's a nice 3.3V rail and happily sprinkles the usual 0.1uF caps here and there plus a big fat
10uF ceramic just to make sure. This brings the combined ESR down way below the minimum ... phssst ... *BANG*.