Can an RTOS guarantee that interrupt latency will never exceed a predefined maximum?

Can an RTOS guarantee that interrupt latency will never exceed a predefined maximum? if so, where do we define this value in the programming?

thanks.

Reply to
NewToFPGA
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No. Not unless the user isn't allowed to disable interrupts or write interrupt service routines. Most RTOSes will quote the maximum latency that the RTOS causes due to it's ISRs and critical sections where interrupts are disabled, but the RTOS can't prevent the user from adding latency.

You don't find that value in the programming. You find it my measuring the execution time of ISRs and critical sections.

--
Grant
Reply to
Grant Edwards

Most likely, with a lot of information and some calculation. It depends on the resource management protocol used. For example, many RTOSes use priority inheritance protocol for which the worst-case critical section time for each task is known.

Agreed.

---Matthew Hicks

Reply to
Matthew Hicks

No, but a competent programmer with a competently-written RTOS can.

As Grant pointed out in his thread, the RTOS can only guarantee that it will respond to OS calls in some maximum time, and that it will only block interrupts for some maximum time. The RTOS writers have no control over what the system programmer does with interrupts or the RTOS, which is where the competent programmer comes in.

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Tim Wescott
Control systems and communications consulting
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Reply to
Tim Wescott

I might point out that this also requires guaranteed instruction timings. They can be long, but they need to be bounded. Caches and pipeline flushes make these hard to determine.

And measuring ISR latency doesn't cut it, unless you measure these effects.

Which is why you see more DSPs and RISCS and fewer pentia in RTOSs.

--
	mac the naïf
Reply to
Alex Colvin

Too true -- but nearly all of the RISC chips, and some of the higher-end DSPs, feature pipelines and/or caches, so that's getting harder, too.

In theory one could calculate this in a sensible way, but it would take deep knowledge of both the processor and RTOS at hand, and it would probably be tedious in the extreme.

--
Tim Wescott
Control systems and communications consulting
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Reply to
Tim Wescott

In Wikipedia it says that modern hardware implements interrupt rate limiting that reduces the amount of time spent servicing interrupts, allowing the processor to spend more time doing useful work. Does it not make the system loose some of the data comming in and not get chance to get processed?

Reply to
NewToFPGA

Interrupt rate limiting is best used in combination with a FIFO in the device. Based on interrupt timing, the device can delay interrupts if they occur too close together, and save up the date in the FIFO. When the FIFO is getting full, it no longer delays the interrupt so the CPU can process all the data at once, reducing overhead.

Reply to
Arlet Ottens

Is it safe to assume that if the expected rate of the interrupts are high and it is most likely that the FIFO going to get full then there is no advantage from Interrupt rate limiting?

Reply to
NewToFPGA

FIFO'ing data to reduce interrupt rates works on comm systems when each bit of data doesn't have to be responded to in an extremely snappy manner, and when the overhead of calling the interrupt is expensive compared to the cost of processing a byte of data - so the processor works on the data in small batches instead of dropping everything, doing one, picking everything up, dropping everything, etc.

--
Tim Wescott
Control systems and communications consulting
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Reply to
Tim Wescott

Do we need to configure Interrupt rate limiting on the processor per application basis? If so, can I configure it on only selective interrupts?

Reply to
NewToFPGA

If a device supports it properly, it can be always be enabled. If the amount of traffic is low, the device won't delay the interrupts (low latency/bandwidth). Only if the interrupt rate is going up, and there is still FIFO space available, the interrupt rate will be limited, which trades off higher latency for higher bandwidth.

Consult the documentation of any devices capable of interrupt rate limiting for exact details of this option.

Reply to
Arlet Ottens

No. But, It can be done by careful design of your system by you.

Karthik Balaguru

Reply to
karthikbalaguru

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