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Caches in embedded systems

Profile the code. If an instruction cache isn't being reloaded then it doesn't need to be associative. If cache use is small enough the difference with a smaller simpler cache will be more noticable.

Yes it will be if you have any 8 byte loops. Profile your code to determine the value for you.

The only problem with embedded cache and pipelined processors subjected to pre-emptive interupts is that the very low frequency of worst case events complicate testing strategy.

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fox
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In this situation you can mess up quite badly.

Assume that the processor has accessed (parts of) the DMA buffer and thus the processor operates on copies found in the cache. Then the DMA transfer will overwrite the DMA buffer and the processor will still operate on the obsolete copies still in the cache. To avoid this, either:

  • disable caching for those addresses used by the DMA buffers

  • the cache hardware must snoop the main memory address bus to detect if any of the addresses generated by the DMA controller is currently cached and invalidate the cache. The cache address translation must monitor both the CPU addresses as well as the main memory bus addresses (generated by the DMA controller), which either requires double comparators or may degrade performance if shared comparators are used.

  • before starting the output DMA transfer, force writeback of all cache lines associated with the DMA buffer by a software routine. After input DMA Transfer-Done interrupt, the cache lines associated with the DMA buffer must be invalidated by a software routine. If these operations can not be done selectively for cache lines associated with the DMA buffers, the whole cache must be turned on and off with each DMA transfer.

Paul

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Paul Keinanen

Any examples of such processor that use 8 byte line size. I typically all processors using 16 or 32. I am wondering what sort of applications and area necessiate an processor with 8 byte line cache line.

shrey

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shrey

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