C6x DMA: using dma_int0 to trigger a dma transaction on dma1

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TI C6x question here:

the dma channels on the C6x can be setup such that they are
synchronized to a number of events (32 total). I have experimenting
with this such at

ext_int7 triggers dma channel 0 to move data
on completion dma0 generates dma_int0 (cpu int8)

I would like to use dma_int0 to kick off another transaction but
with dma channel 1. in short have dma channel 1 synchronized to
the dma0's complete interrupt.

the first part is functioning as expected, second part is where
the problem lies. I know the dma0 complete interrupt is generated
since I have a handler chained to it, but its not triggering a
transaction on dma channel 1.

Has anyone done something like this?
Ill post code if anyone is interested.

Thanks



Re: C6x DMA: using dma_int0 to trigger a dma transaction on dma1
Quoted text here. Click to load it


/******************/
int    wdDmaCtrl0=0,wdDmaCtrl1;

    /*halt DMA0 and DMA1*/
    DMA0_PRIMARY_CTRL=DMA_STOP_VAL;
    DMA1_PRIMARY_CTRL=DMA_STOP_VAL;
    
    /*initialize DMA0 to transfer on int 7 and to reload
 using counterA and globalB*/

    DMA0_SECONDARY_CTRL=(1<<RSYNC_CLR)|(1<<BLOCK_IE);
    DMA0_SRC_ADDR=(unsigned int)LCL_FIFO_IO;
    DMA0_DEST_ADDR=(unsigned int)LCL_INT_DATA_MEM;
    DMA0_XFER_COUNTER=BUFFER_SIZE;
    
    DMA_GCR_A=BUFFER_SIZE;
    DMA_GADDR_B=(unsigned int)LCL_INT_DATA_MEM;
    
    /*initialize DMA1 to transfer on dmaint0 and to
     reload using counterB and globalC*/
    DMA1_SECONDARY_CTRL=(1<<RSYNC_CLR);
    DMA1_SRC_ADDR=(unsigned int)LCL_INT_DATA_MEM;
    DMA1_DEST_ADDR=(unsigned int)LCL_FIFO_XX;
    DMA1_XFER_COUNTER=BUFFER_SIZE;
    
    DMA_GCR_B=BUFFER_SIZE;
    DMA_GADDR_C=(unsigned int)LCL_INT_DATA_MEM;
    
    /*kick off the process*/
    wdDmaCtrl1=
(DMA_AUTO_START_VAL<<START)|(DMA_ADDR_INC<<SRC_DIR)|(DMA_CNT_RELOADB<<CNT_RELOAD);
    
wdDmaCtrl1|=(SEN_DMA_INT0<<RSYNC)|(DMA_DMA_PRI<<PRI)|(1<<FS)|(DMA_RELOAD_GARC<<DST_RELOAD);
    DMA1_PRIMARY_CTRL=wdDmaCtrl1;
    
    wdDmaCtrl0=
(DMA_AUTO_START_VAL<<START)|(DMA_ADDR_INC<<DST_DIR)|(SEN_EXT_INT7<<RSYNC);
    
wdDmaCtrl0|=(DMA_DMA_PRI<<PRI)|(1<<TCINT)|(1<<FS)|(DMA_RELOAD_GARB<<DST_RELOAD);
    DMA0_PRIMARY_CTRL=wdDmaCtrl0;


/********************************************/

dma0 operates as expected and theres a call to my dma0_int8
(dma complete) isr. But dma1 isnt being triggered on dma0's
completion as expected.

so
data is read out of fifo_IO into idram (dma0)
but not from idram into fifo_xx        (dma1)

Any ideas?

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