Bringing up AMD Au1000

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Hi everybody,

I got a development board from AMD DB1000 with the Alchemy AU1000
processor.
I use a Macraigor Wiggler for MIPS and the OCD Commander for
debugging.
I try to bring up the board with an invalid flash content, but I fail.

I set all necessary registers (See script) and download a valid
ELF-file, but when I run it by the debugger it seems to stall and jump
to the reset vector, resulting in a restart from the invalid flash. If
I run a valid flash content from the debugger it also fails when I
stop the processor during start and continue it. When I leave it
running without stopping it, it succeeds.

Is there some known bug and/or workaround for running code with the
OCD Commander? Why does it fail when I run valid code from the flash
which suceeds when I do not stop and continue the boot process by the
debugger?

Here is the script which I execute when I manually load it:
; Script für die Speicher- und CPU-Initialisierung
; für RAM-Ausführung von Programmen
;
; Reset CPU and set endian mode
;
reset                        ; Reset target
MIPSENDIAN LITTLE            ; Switch to little endian debugger and
board
;
; Initialize CPU registers
;
CP0STATUS = $00400000        ; Establish status register -
AU1000Reset_rev1.2.pdf
CONFIG0   = $80080083        ; Set Config0 --> Config0[OD] also set
WATCHLO   = $00000000        ; Disable watchpoint ressources
IWATCHLO  = $00000000        ; Disable watchpoint ressources
PERFCNT   = $00000000        ; Disable Performance Counter
DEBUG     = $00000000        ; Disable EJTAG
CAUSE     = $00800000        ; Cause[IV] set to permit the interrupt
execution vector to belocated at its own vector address
; Initialize TLBs

; Establish PLL frequency
; Base Address: $11900000 KSEG1 $B1900000
; Offset   Register name   Description
;-------------------------------------------------------------------------------------------------
; 00000020 sys_freqctrl0   Controls (source, enable and divider)
frequency generators 0,1 and 2
; 00000024 sys_freqctrl1   Controls (source, enable and divider)
frequency generators 3,4 and 5
; 00000028 sys_clksrc      Controls (source and divider) the derived
clocks
; 00000060 sys_cpupll      Changes the CPU PLL frequency
; 00000064 sys_auxpll      Changes auxiliary PLL frequency
word $b1900060 = $00000021   ; Change CPU clock to 396 MHz

word $b1900064 = $0000000C   ; Change AUX-PLL to 144 MHz


;
; Enable 32kHz oscillator
; Base Address: $11900000 KSEG1 $B1900000
; Offset   Register name   Description
;-------------------------------------------------------------------------------------------------
; 00000014 sys_cntrctrl    Control register for TOY and RTC
word $b1900014 = $00000160   ; Copied from Yamon


; Initialize static memory controller
; Base Address: $14000000 KSEG1: $B4000000
; Offset   Register name   Description
;-------------------------------------------------------------------------------------------------
; 00000000 mem_sdmode0     SDRAM chip select mode configuration
register (timing and functionality)
; 00000004 mem_sdmode1    
; 00000008 mem_sdmode2    
; 0000000C mem_sdaddr0     SDCS addres configuration and enable
; 00000010 mem_sdaddr1    
; 00000014 mem_sdaddr2    
; 00000018 mem_sdrefcfg    Refresh configuration and Timing
; 0000001C mem_sdprecmd    Issue PRECHARGE to all enabled SDRAM chip
selects
; 00000020 mem_sdautoref   Issue AUTO REFRESH to all enabled SDRAM
chip selects
; 00000024 mem_sdwrmd0     Write data to SDCSn SDRAM mode
configuration register
; 00000028 mem_sdwrmd1    
; 0000002C mem_sdwrmd2
; 00000030 mem_sdsleep     Force SDRAM into self refresh mode
; 00000034 mem_sdsmcke     Toggle SMROMCKE pin

; Copy from Yamon
word $b4000000 = $005522aa   ; No SyncFlash,
SDRAM/SyncFlash-Operation, 4-bank SDRAM, 12 Rows, 9 Columns
word $b4000004 = $005522AA   ; SDRAM/SyncFlash-Operation, 4-bank
SDRAM, 12 Rows, 9 Columns
word $b4000008 = $00000000   ; CS2 - nicht verwendet
word $b400000C = $001003f8   ; CS0 gemappt auf $00000000
word $b4000010 = $001023f8   ; CS1 gemappt auf $80000000
word $b4000014 = $00000000   ; CS2 - nicht verwendet
word $b4000018 = $66000c24   ; Timing:
; The refresh interval is for each individual refresh so for a system
with a row
; address size of 12 (4096 rows) and memory with a refresh time of 64
ms (all rows),
; the individual refresh interval will be 15.7 µs (64 ms/4096). With a
system bus clock of 198 MHz,
; the RI value should be 0xC24 (15.7 µs / (1/198 MHz).
word $b4000020 = $00000000   ; Initiate Auto-Refresh manually

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