Boot Sequence for Sharp Micro Controller LH754xx (LH75411, LH75410, LH75401, LH75400)

I assume the Sharp "bluestreak library" supports these chips? (I use the LH79520). It's a useful resource for getting things up and running, pinching initialisation sequences, register names etc.

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John Devereux

Hi,

yes, this is right. Actually I am trying to use the startup sequence given in the library. Nevertheless, I am facing some problems. I compiled the kev..._startup.asm and linked it to my C programme. The assembly source shows this:

Disassembly of section .text:

00000000 ea000006 b 00000020 00000004 ea000004 b 0000001c 00000008 ea000003 b 0000001c 0000000c ea000002 b 0000001c 00000010 ea000001 b 0000001c 00000014 e1a00000 nop (mov r0,r0) 00000018 e51ffff0 ldr pc, [pc, #-4080] ; fffff030

0000001c ea000001 b 00000028

00000020 e59f00e8 ldr r0, [pc, #232] ; 00000110

00000024 e1a0f000 mov pc, r0

00000028 eafffffe b 00000028 0000002c eb00002b bl 000000e0 00000030 eb000032 bl 00000100 00000034 eb000028 bl 000000dc 00000038 eb000026 bl 000000d8 0000003c eb000012 bl 0000008c 00000040 eb000002 bl 00000050 00000044 eb00000c bl 0000007c 00000048 e59f00c4 ldr r0, [pc, #196] ; 00000114

0000004c e1a0f000 mov pc, r0

00000050 e59f00c0 ldr r0, [pc, #192] ; 00000118 [...]

I am loading this into the internal SRAM via JTAG and step through it. Since my FlashRam is not working yet, I have to start the programme at address 0x0 manually (BTW: which processor mode should I use?). As you see in the code, from adress 0x0 it jumps to 0x20 which holds the instruction "ldr r0, [pc, #232]". Actually, this instruction fails! The JTAG programme (OCD Debugger) says: "Processor running" and if I halt the device, the cpu shows an undefined state (Processor mode is

0x0).

How this? Did I forget something? Stack settings probably? But all this should be handled by the startup sequence!

Any help is appreciated!

Daniel

Sounds more like a problem with the debugger to me. My code starts like this (remember it's for the LH79520 though!):

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.equ MODE_USR ,0x10 .equ Mode_FIQ ,0x11 .equ Mode_IRQ ,0x12 .equ Mode_SVC ,0x13 .equ Mode_ABT ,0x17 .equ Mode_UNDEF ,0x1B .equ Mode_SYS ,0x1F /* only available on ARM Arch. v4 */ .equ I_Bit ,0x80 .equ F_Bit ,0x40

/* Locations of our memory system */ .equ MEMORY_Limit ,0x60008000 .equ RuntimeStackTop ,0+__ram_size /* svc mode stack (our main runtime stack)

*/ /* can use whole of iram (0x8000 bytes) for runtime isr stacks and bss */ .equ Stack_Limit ,MEMORY_Limit - 0x10 .equ SVC_Stack ,Stack_Limit /* = 0x200 bytes */ .equ ABT_Stack ,SVC_Stack - 0x200 /* = 0x200 bytes */ .equ UNDEF_Stack ,ABT_Stack - 0x200 /* = 0x200 bytes */ .equ IRQ_Stack ,UNDEF_Stack - 0x200 /* = 0x200 bytes */ .equ FIQ_Stack ,IRQ_Stack - 0x200 /* = 0x200 */ .equ USR_Stack ,FIQ_Stack - 0x200 /* = XXX bytes */

_runtime: _reset: b init_stacks _undefined: b _undefined _swi: b osSWIint _prefetch_abort: b _prefetch_abort _data_abort: b _data_abort nop /* reserved location */ _irq: /* take vectored interrupt */ ldr pc,[pc,#-0xff0] _fiq: b _fiq_handler init_stacks: /* --- Initialize stack pointer registers */ /* Enter IRQ mode and set up the IRQ stack pointer */ MOV r0, #Mode_IRQ orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =IRQ_Stack

/* Enter FIQ mode and set up the FIQ stack pointer */ MOV r0, #Mode_FIQ orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =FIQ_Stack

/* Enter ABT mode and set up the ABT stack pointer */ MOV r0, #Mode_ABT orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =ABT_Stack

/* Enter IRQ mode and set up the IRQ stack pointer */ MOV r0, #Mode_UNDEF orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =UNDEF_Stack

/* Set up the SVC stack pointer last and return to SVC mode */ MOV r0, #Mode_SVC orr r0,r0,#I_Bit orr r0,r0,#F_Bit /* No interrupts */ MSR cpsr_c, r0 LDR sp, =SVC_Stack

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John Devereux

John,

thanks! I will try your stack setup. I am still supsecting the stack...

stack) */