Backup battery for AT91SAM9261

Looking at the data sheet for the AT91SAM9261, it says the back up supply voltage range is 1.08 to 1.32 volts with a current of 2.5 microAmps. This could be supplied by a watch battery except I have no idea how to regulate the voltage to this range without draining the battery from the regulator quiessent current. I don't recall seeing any circuits that could provide a regulated voltage and not draw at least 10 times this much current.

What was Atmel thinking when they drew up these plans for a battery backed RTC?

Or am I missing something obvious, like a 1.2 volt, low self drain battery that is perfect for this job?

Reply to
rickman
Loading thread data ...

Perhaps one of these very high capacitance capacitors, charge it to 1.3 V, 1F @ 2.5 uA will lose 0.25 V for > 10 days, I believe I have seen capacitors much larger than that.

Making a regulator which cosumes 1 uA or so will be no rocket science either.

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

formatting link

------------------------------------------------------

Reply to
Didi

Possibly it was originally designed for use with mercuric oxide batteries, which have a no-load voltage of 1.35 volts. Mercury-formula batteries are no longer legal in the USA, and this has been a problem for (vintage) camera buffs. The typical solution is to take a 1.5V alkaline cell and add a diode to drop the voltage, but this probably won't work well with a 2.5 uA load.

Of course, a rechargeable NiMH or NiCd cell is 1.2V... You could trickle charge it when "main" power is available, and run from it for the RTC function when "off". A fully charged 500 mAH cell would run a

2.5 uA load for 200,000 hours, or 22 years, if not for the ~1% self- discharge. You would certainly get a few months before you would need to supply a recharge...

--Gene

Reply to
Gene S. Berkowitz

Isn't that a pretty large battery for a clock backup? But the self discharge is the real issue. I just find it odd that they would design the power circuit for a real time clock to be anything other than compaitble with 1.5 volt Silver Oxide found in watches or 3 volt lithium cells found in pretty much all the other stuff that needs a backup battery. If it needs an LDO to work with standard batteries, then shove that inside the chip. Isn't integration what these chips are all about?

Reply to
rickman

Since it is in a 0,13u process, the core voltage is limited to 1.2V. The integrated LDO has 30-40uA inherent power consumption. The external voltage regulator has 1 uA power consumption. Different processes you know.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

The data says this: ? VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. ? VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal.

So, seems it powers not just the OSC, but some other stuff as well, and that will be in the same process as the core - thus the tight VddBU Spec. Wonder what the ESD rating on the VddBU is ? - this could need care, if designing to replace batteries in the field.

If you do find a uA region regulator, that is happy with Vin=1.5V, and Vo = 1.2V, AND continues to draw the low uA whilst in dropout, let us know.

-jg

Reply to
Jim Granville

I understand about processes, but a regulator that powers a 70 mA core would draw more current than one that powers a 2.5 uA RTC. I can't imagine that you could not have put a regulator in the circuit for a

1.5 volt cell with a decent power consumption. This sort of attention to detail is what makes a good design great. If I have to add a bunch of different small parts to an MCU like this, it can make me want to use a different MCU. I can actually get an RTC for the same price as a typical LDO.

BTW, as long as I have your attention, am I correct in thinking that this part can not boot from NAND flash? The data sheet seems to say that I have to use either standard NOR flash (or some other directly addressable memory) or a serial SPI flash. I have not read the entire data sheet yet. In particular I have not real all about the memory interface. If I let the CPU boot from memory, will it handle the NAND flash interface so that it looks like random access NOR flash and the CPU can boot from it? I am used to treating NAND flash like a block memory device that is not directly executable and must be copied to RAM memory.

Reply to
rickman

Maybe there is no suitable LDO available in that specific process... The 0.13u has not been around for that long inside Atmel.

No, You can put U-Boot in a *small* serial flash (1-2 Mbit), and then you continue from there. NAND flash boot is a possibility for future chips.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

Perhaps Atmel should characterize a Series Diode + Watch battery solution, and publish that as a practical battery solution ?

Or a PNP transistor, and two resistors ? - fine control over the voltage drop & more current tolerance, at the expense of some static current. Some ESD comments would be good too :)

-jg

Reply to
Jim Granville

I understand that the processor can boot from the serial flash. So it can not boot from a NAND flash. Again, I consider this a shortcoming of the chip that requires yet another small chip to be placed around the CPU to make it functional.

The list grows...

Reply to
rickman

Only if you actually need to have the NAND Flash. normally people are keeping the kernel and the file system in that small serial flash.

Many build Embedded Linux systems with downto 4 MB of Flash or even 2 MB. Won't do too much, but there is significant volume in these applications. You can get 8 MB in the same form factor today and 16/32 MB are in development.

Small size NAND flash are dying out, so even if you get much more memory w NAND, that won't help you if you dont use it.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

I don't know where you are coming from. I don't have any trouble using fully the NAND flash in a design. Heck, the FPGA on the board alone can use up to a couple of MB of flash. What I am trying to do is to not have to add a NAND flash for the capacity and then also add another flash for code storage. That just seems so wasteful of cost and board space.

There are a number of ARM devices that will boot from NAND flash and that will be shown on the next ARM chart I put up on

formatting link

Reply to
rickman

Yes if I compile the Buildroot enabling everything in the system, the flash disk becomes 3-400 MB. Then again, I see most or all large volume designs (>= 100ku/year) I know about will fit into 4 or 8 MB. There are also several designs where 256 kB Flash is quite enough. They want a low power micro which runs faster than allowed by on chip flash solutions and like the large internal SRAM memory.

So is booting from NAND a bad thing? of course not.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.