AVR with Parallel Flash Memory

That's lucky...... all the info you need is in the Atmel data sheets, but I suspect you don't understand what is in front of you. Have you thouight about SPI flash ?

I

Parallel is used due to the requirements of the project.

You're right, I don't fully understand everything within the datasheets hence why I am asking for a little bit of help to gain better understanding.

I'm not in a electronics background for work/academic the only resource I have when I don't fully understand something is community forums and books.

It is quite easy to insert enough no operation instructions so I can be sure that I am within the correct time frames, I simply want to be able to calculate it properly. I know a few issues that would effect this is things such as the sync latching.

Regards.

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nd

You mean other than 1/12000000 or 0.833333333333333333333333333333ns?

,

If the clock pulse is square and the latch is level activated, it will latch exactly half a cycle.

an

Can't help you without knowing exactly what you are trying to do.

I'm pretty sure he means something other than

0.833333333333333333333333333333ns, my guess is about two orders of magnitude more than that.

ms

a and

e

Yes, you are correct. 0.833333333333333333333333333333 microsec.

waveforms

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Thanks linnix,

The half cycle is the minimum case, worst is one and half cycles. The datasheet also says that out instruction sets sync latch, however there are other ways of setting the port value such as sbi/cbi.

I was hoping that someone could explain better how it effects the delay when setting a port value.

The AVR is directly connected to the flash. It sets the ports (address, data, control) in order to read or write from/to the flash memory. My current code works however I know its only because I have inserted extra nops to make sure I have the minimum hold/setup times for the waveform.

With better understanding of how long each cycle is, this sync latch issue I would be able to modify my code to remove these redundant nops as I would be able to calculate the correct timing.

Regards.

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And the correct answer is.... 83.3 ns!

This is a little mangled. If you are talking to conventional parallel flash, that should need minimal timing patches on Read, but it will need care on Write. ie if you READ: Define all address values Float the IO port Pull OEN low [NOP insert point] Read BUS value Pull OEN Hi

That will easily meet Address setup time, and leaves any pipeline effects for bus turnaround. It's easy to check if you know the expected read value.

Write is going to need a scheme to load a page, or partial page, and then time, or poll, for the Write completion. Polling is probably the more revision-safe approach.

-jg

If you create the bus cycles manually with a 12MHz AVR, you must have a very slow flash before you need to insert NOPs to get the timing right. What's the speed of the flash chip you're using? To give you an idea: I am currently working with a PIC18 running at 24MHz (at gun point, I must admit) and the flash has an access time of 100ns. No NOPs required and the total transfer speed is dead slow at 75kbyte/s....

Meindert

ery

o

It's not so much Taa timing, as port-pipeline effects

- on single-cycle parts, often you cannot read immediately after a write, if you want read to reflect that write.

This post over in Avrfreaks:

["When switching between output and input, I found 2 cycles were needed at 20MHz in order to read the port data. I use 3 NOPs just to play it safe."]

NMMX skrev:

That is real strange. It is a significant disadvantage to use parallell vs SPI flash, so if I were you, I would go back and investigate why it is a requirement. Easiest is to use an 8 bit flash memory and an AVR with an external bus, like the ATmega1281 or XMEGA. Then you need to demultiplex the bus, and thats it. Chip select controlled by an I/O pin, if that is the only thing on the bus.

--
Best Regards
Ulf Samuelsson
These are my own personal opinions, which may
or may not be shared by my employer Atmel Nordic AB

NMMX skrev:

That is real strange. It is a significant disadvantage to use parallell vs SPI flash, so if I were you, I would go back and investigate why it is a requirement. Easiest is to use an 8 bit flash memory and an AVR with an external bus, like the ATmega1281 or XMEGA. Then you need to demultiplex the bus, and thats it. Chip select controlled by an I/O pin, if that is the only thing on the bus.

--
Best Regards
Ulf Samuelsson
These are my own personal opinions, which may
or may not be shared by my employer Atmel Nordic AB