Yes, the PSoC3. Their Logic is very CPLD like, with a product term macrocell, with a fan-in of 12 (compared with 40 for Atmel CPLDs and 36-40 for others)
I think that is quite different from the earlier PSoC1 devices, which were more basic menu-choice based blocks. That put me off them, as well as the orphan core.
The reports base on 192 of these D/T macrocells, and you can access all this from Verilog - so the logic is quite accessible.
In the tests I did, I found that as long as I kept the fanin below that 12 ceiling, then the logic compiles behaved as expected. ( of course, Cypress mention none of this )
When you say fan in of 12, you don't mean product terms do you? That would be a very adequate number of product terms. I don't recall seeing any CPLDs with up to 40 product terms. If it is just 12 inputs, then it all depends on how they are connected. I will have to look at the new PSoC devices a bit more, but I seem to recall they are hard to learn since the focus is on using their magic GUI and less on just letting you at the native hardware.
Too bad I am a VHDL guy! Maybe I'll download their tool and try it out. That seems to be the way they want you to learn the parts. There is still the issue of price. Their parts are more expensive then the FPGAs I am currently using.
FanIn is effectively the width of the wide AND gate, so is the number of signals that can be Boolean ANDed. When you include some Enables & clocks, it means around 8-9-10 bit counters are the best fit.
Looking at the report file, I see that FanIn goes up to 12, (I rewrote things to keep at
Typically the utility of macrocells are not limited by the number inputs to the and gates. They are normally as wide as the number of signals in a bank so that all inputs can feed all product terms and there is no signal routing problems within a given block. The macrocell capability is limited by the number of product terms that go into each or gate. In most CPLDs this is fixed for a given macrocell, but can vary across the macrocells so that the few functions that need more logic can have it, but the smaller logic functions can fit in the rest of the macrocells. A few logic families can share product terms across macrocells or at least allow some product terms to be partitioned to different macrocells, but that is the exception I believe.
Ok, that is a lot more clear. I guess I don't need to know exactly how they block out their logic, the tools will or at least should optimize that for me.
I've never been a fan of CPLDs myself, primarily because of the cost per logic element. The Lattice Flash FPGAs seem to do a lot better in that regard. There is some irony here. Cypress used to have an interesting line of CPLD/FPGA devices, flash based, IIRC.
I thought the PSoC3 parts were available and had pricing, no? I am waiting for the PSOC5 parts myself. But then I have been waiting for over two and a half years now! I'm not holding my breath. Imagine how many design wins they could have achieved if they had come out with the devices a year and a half ago like they planned! They have been saying Q2 of 2010 for months now. They have less than 30 days left to meet their deadline.
Depends on the design. It happens that on the last 2 I've done, the FanIn was the ceiling I banged into. (and this on Fanin 40 devices)
In the Cypress devices, the fanin of 12 I'd call unusually low, and so it will be more of an issue. Certainly I had to modify my design to better match the resource.
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