Atmel AVR assembler

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Have to write some AVR code and therefore have read the
AVR Instruction Set manual and tried the assembler included
in  AVR studio. I think the used syntax is completely
unusable, so I decided to write my own assembler. A very
first version can be downloaded from:

ftp://137.193.64.130/pub/assembler/adela.zip

Maybe there are some AVR experts who can give some suggestions
for an improvement or are even willing to do some testing.

The used syntax:


*******************************************************************
*                     Instruction set                             *
*******************************************************************

add.b      ri,rj               ; i,j=0..31                  ADD    
addc.b     ri,rj               ; i,j=0..31                  ADC    
addq.w     #imm6u,ri|rj        ; j24%,26,28,30  i=k+1       ADIW    
and.b      #imm8,rj            ; j16%..31                   ANDI    
and.b      ri,rj               ; i,j=0..31                  AND    
asr.b      #1,rj               ; j=0..31                    ASR    
                                                            
bcc.b      label               ; C=0                        BRCC    
bcs.b      label               ; C=1                        BRCS    
beq.b      label               ; Z=1                        BREQ    
bge.b      label               ; S=(N eor V) = 0            BRGE    
bhcc.b     label               ; H=0                        BRHC    
bhcs.b     label               ; H=1                        BRHS    
bhs.b      label               ; C=0                        BRSH    
bic.b      label               ; I=0                        BRID    
bis.b      label               ; I=1                        BRIE    
blo.b      label               ; C=1                        BRLO    
blt.b      label               ; S=(N eor V) = 1            BRLT    
bmi.b      label               ; N=1                        BRMI    
bne.b      label               ; Z=0                        BRNE    
bpl.b      label               ; N=0                        BRPL    
btc.b      label               ; T=0                        BRTC    
bts.b      label               ; T=1                        BRTS    
bvc.b      label               ; V=0                        BRVC    
bvs.b      label               ; V=1                        BRVS    
                                                            
br.w       label                                            RJMP    
bsr.w      label                                            RCALL  
                                                            
cmp.b      #imm8,rj            ; j16%..31                   CPI    
cmp.b      ri,rj               ; i,j=0..31                  CP      
cmpc.b     ri,rj               ; i,j=0..31                  CPC    
dec.b      rj                  ; j=0..31                    DEC    
eor.b      ri,rj               ; i,j=0..31                  EOR    
fmuls.b    ri,rj,r1|r0         ; i,j16%..23                 FMULS  
fmulsu.b   ri,rj,r1|r0         ; i,j16%..23                 FMULSU  
fmulu.b    ri,rj,r1|r0         ; i,j16%..23                 FMUL    
halt                                                        BREAK  
inc.b      rj                  ; j=0..31                    INC    
                                                            
jmp.l      (*|r31|r30)                                      EIJMP  
jmp.l      label                                            JMP    
jmp.w      (r31|r30)                                        IJMP    
jsr.l      (*|r31|r30)                                      EICALL  
jsr.l      label                                            CALL    
jsr.w      (r31|r30)                                        ICALL  
                                                            
lsr.b      #1,rj               ; j=0..31                    LSR    
                                                            
move.b     #imm8,rj            ; j16%..31                   LDI    
move.b     ri,rj               ; i,j=0..31                  MOV    
move.b     adr,rj              ; j=0..31                    LDS    
move.b     ri,adr              ; i=0..31                    STS    
                                                            
move.b         (r27|r26),rj    ; j=0..31                    LD      
move.b     imm6(r29|r28),rj    ; j=0..31                    LDD    
move.b     imm6(r31|r30),rj    ; j=0..31                    LDD    
move.b     ri,    (r27|r26)    ; i=0..31                    ST      
move.b     ri,imm6(r29|r28)    ; i=0..31                    STD    
move.b     ri,imm6(r31|r30)    ; i=0..31                    STD    
                                                            
move.b     -(r27|r26),rj       ; j=0..31                    LD      
move.b     -(r29|r28),rj       ; j=0..31                    LD      
move.b     -(r31|r30),rj       ; j=0..31                    LD      
move.b     ri,-(r27|r26)       ; i=0..31                    ST      
move.b     ri,-(r29|r28)       ; i=0..31                    ST      
move.b     ri,-(r31|r30)       ; i=0..31                    ST      
                                                            
move.b     (r27|r26)+,rj       ; j=0..31                    LD      
move.b     (r29|r28)+,rj       ; j=0..31                    LD      
move.b     (r31|r30)+,rj       ; j=0..31                    LD      
move.b     ri,(r27|r26)+       ; i=0..31                    ST      
move.b     ri,(r29|r28)+       ; i=0..31                    ST      
move.b     ri,(r31|r30)+       ; i=0..31                    ST      
                                                            
move.b     +(sp),rj            ; j=0..31                    POP    
move.b     rj,(sp)-            ; j=0..31                    PUSH    
                                                            
move.b     ?adr6,rj            ; adr6=0..63 j=0..31         IN      
move.b     ri,?adr6            ; adr6=0..63 i=0..31         OUT    
                                                            
                                                            
move.bit   rj[imm3],sr[6]      ; j=0..31                    BST    
move.bit   sr[6],rj[imm3]      ; j=0..31                    BLD    
move.bit   #0,sr[imm3]         ; ITHSVNZC                   BCLR    
move.bit   #1,sr[imm3]         ; ITHSVNZC                   BSET    
move.bit   #0,?adr5[imm3]      ; adr5=0..31                 CBI    
move.bit   #1,?adr5[imm3]      ; adr5=0..31                 SBI    
                                                            
move.w     ri|rj,rk|rm         ; j,m=0,2,..,30 i=j+1 k=m+1  MOVW    
                                                            
movePM.b   (r31|r30),r0                                     LPM    
movePM.b   (r31|r30),rj        ; j=0..31                    LPM    
movePM.b   (r31|r30)+,rj       ; j=0..31                    LPM    
movePM.b   (*|r31|r30),r0                                   ELPM    
movePM.b   (*|r31|r30),rj      ; j=0..31                    ELPM    
movePM.b   (*|r31|r30)+,rj     ; j=0..31                    ELPM    
                                                            
muls.b     ri,rj,r1|r0         ; i,j16%..31                 MULS    
mulsu.b    ri,rj,r1|r0         ; i,j16%..23                 MULSU  
mulu.b     ri,rj,r1|r0         ; i,j=0..31                  MUL    
neg.b      rj                  ; j=0..31                    NEG    
nop                                                         NOP    
not.b      rj                  ; j=0..31                    COM    
or.b       #imm8,rj            ; j16%..31                   ORI    
or.b       ri,rj               ; i,j=0..31                  OR      
prog                                                        SPM    
rocr.b     #1,rj               ; j=0..31                    ROR    
rol.b      #4,rj               ; j=0..31                    SWAP    
ror.b      #4,rj               ; j=0..31                    SWAP    
rte                                                         RETI    
rts                                                         RET    
                                                            
skipeq.b   ri,rj               ; i,j=0..31                  CPSE    
skipeq.bit #0,?adr5[imm3]      ; adr5=0..31                 SBIC    
skipeq.bit #0,rj[imm3]         ; j=0..31                    SBRC    
skipeq.bit #1,?adr5[imm3]      ; adr5=0..31                 SBIS    
skipeq.bit #1,rj[imm3]         ; j=0..31                    SBRS    
                                                            
sleep                                                       SLEEP  
sub.b      #imm8,rj            ; j16%..31                   SUBI    
sub.b      ri,rj               ; i,j=0..31                  SUB    
subc.b     #imm8,rj            ; j16%..31                   SBCI    
subc.b     ri,rj               ; i,j=0..31                  SBC    
subq.w     #imm6u,ri|rj         ; j24%,26,28,30  i=k+1      SBIW    
wdog_reset                                                  WDR    


BRBC    -> branch Befehle                                        
CBR     -> and.b                                        
CLR     -> eor.b                                        
CLC,CLH,CLI,CLN,CLS,CLT,CLV,CLZ -> move.bit                              
LSL     -> add.b                                        
ROL     -> addc.b                                        
SBR     -> or.b                                        
SEC,SEH,SEI,SEN,SES,SET,SEV,SEZ -> move.bit                              
SER     -> or.b                                        
TST     -> and.b                                        




*******************************************************************
*                     Opcode list                                 *
*******************************************************************


0000 0000 0000 0000  nop
0000 0001 jjjj iiii  move.w     ri|rj,rk|rm     ; j,m=0,2,..,30  i=j+1 k=m+1
0000 0010 jjjj iiii  muls.b     ri,rj,r1|r0         ; i,j16%..31
0000 0011 0jjj 0iii  mulsu.b    ri,rj,r1|r0         ; i,j16%..23
0000 0011 0jjj 1iii  fmulu.b    ri,rj,r1|r0         ; i,j16%..23
0000 0011 1jjj 0iii  fmuls.b    ri,rj,r1|r0         ; i,j16%..23
0000 0011 1jjj 1iii  fmulsu.b   ri,rj,r1|r0         ; i,j16%..23
0000 01ij jjjj iiii  cmpc.b     ri,rj               ; i,j=0..31
0000 10ij jjjj iiii  subc.b     ri,rj               ; i,j=0..31
0000 11ij jjjj iiii  add.b      ri,rj               ; i,j=0..31

0001 00ij jjjj iiii  skipeq.b   ri,rj               ; i,j=0..31
0001 01ij jjjj iiii  cmp.b      ri,rj               ; i,j=0..31
0001 10ji jjjj iiii  sub.b      ri,rj               ; i,j=0..31
0001 11ij jjjj iiii  addc.b     ri,rj               ; i,j=0..31

0010 00ij jjjj iiii  and.b      ri,rj               ; i,j=0..31
0010 01ij jjjj iiii  eor.b      ri,rj               ; i,j=0..31
0010 10ji jjjj iiii  or.b       ri,rj               ; i,j=0..31
0010 11ij jjjj iiii  move.b     ri,rj               ; i,j=0..31

0011 #### jjjj ####  cmp.b      #imm8,rj            ; j16%..31
0100 #### jjjj ####  subc.b     #imm8,rj            ; j16%..31
0101 #### jjjj ####  sub.b      #imm8,rj            ; j16%..31
0110 #### jjjj ####  or.b       #imm8,rj            ; j16%..31
0111 #### jjjj ####  and.b      #imm8,rj            ; j16%..31

10#0 ##0j jjjj 0###  move.b     imm6(r31|r30),rj    ; j=0..31
10#0 ##0j jjjj 1###  move.b     imm6(r29|r28),rj    ; j=0..31
10#0 ##1i iiii 0###  move.b     ri,imm6(r31|r30)    ; i=0..31
10#0 ##1i iiii 1###  move.b     ri,imm6(r29|r28)    ; i=0..31

1001 000j jjjj 0000  move.b     adr,rj              ; j=0..31
#### #### #### ####
1001 000j jjjj 0001  move.b     (r31|r30)+,rj       ; j=0..31
1001 000j jjjj 0010  move.b     -(r31|r30),rj       ; j=0..31
1001 000j jjjj 0100  movePM.b   (r31|r30),rj        ; j=0..31
1001 000j jjjj 0101  movePM.b   (r31|r30)+,rj       ; j=0..31
1001 000j jjjj 0110  movePM.b   (*|r31|r30),rj      ; j=0..31
1001 000j jjjj 0111  movePM.b   (*|r31|r30)+,rj     ; j=0..31
1001 000j jjjj 1001  move.b     (r29|r28)+,rj       ; j=0..31
1001 000j jjjj 1010  move.b     -(r29|r28),rj       ; j=0..31
1001 000j jjjj 1100  move.b     (r27|r26),rj        ; j=0..31
1001 000j jjjj 1101  move.b     (r27|r26)+,rj       ; j=0..31
1001 000j jjjj 1110  move.b     -(r27|r26),rj       ; j=0..31
1001 000j jjjj 1111  move.b     +(sp),rj            ; j=0..31
1001 001i iiii 0000  move.b     ri,adr              ; i=0..31
#### #### #### ####
1001 001i iiii 0001  move.b     ri,(r31|r30)+       ; i=0..31
1001 001i iiii 0010  move.b     ri,-(r31|r30)       ; i=0..31
1001 001i iiii 1001  move.b     ri,(r29|r28)+       ; i=0..31
1001 001i iiii 1100  move.b     ri,(r27|r26)        ; i=0..31
1001 001i iiii 1101  move.b     ri,(r27|r26)+       ; i=0..31
1001 001i iiii 1010  move.b     ri,-(r29|r28)       ; i=0..31
1001 001i iiii 1110  move.b     ri,-(r27|r26)       ; i=0..31
1001 001j jjjj 1111  move.b     rj,(sp)-            ; j=0..31

1001 010j jjjj 0000  not.b      rj                  ; j=0..31
1001 010j jjjj 0001  neg.b      rj                  ; j=0..31
1001 010j jjjj 0010  rol.b      #4,rj               ; j=0..31
1001 010j jjjj 0010  ror.b      #4,rj               ; j=0..31
1001 010j jjjj 0011  inc.b      rj                  ; j=0..31
1001 010j jjjj 0101  asr.b      #1,rj               ; j=0..31
1001 010j jjjj 0110  lsr.b      #1,rj               ; j=0..31
1001 010j jjjj 0111  rocr.b     #1,rj               ; j=0..31

1001 0100 0### 1000  move.bit   #1,sr[imm3]         ; ITHSVNZC
1001 0100 1### 1000  move.bit   #0,sr[imm3]         ; ITHSVNZC
1001 0101 0000 1000  rts
1001 0101 0001 1000  rte
1001 0101 1000 1000  sleep
1001 0101 1001 1000  halt
1001 0101 1010 1000  wdog_reset
1001 0101 1100 1000  movePM.b   (r31|r30),r0
1001 0101 1101 1000  movePM.b   (*|r31|r30),r0
1001 0101 1110 1000  prog

1001 0100 0000 1001  jmp.w      (r31|r30)
1001 0101 0001 1001  jsr.l      (*|r31|r30)
1001 0100 0001 1001  jmp.l      (*|r31|r30)
1001 0101 0000 1001  jsr.w      (r31|r30)

1001 010j jjjj 1010  dec.b      rj                  ; j=0..31
1001 010# #### 110#  jmp.l      label
#### #### #### ####
1001 010# #### 111#  jsr.l      label
#### #### #### ####

1001 0110 ##jj ####  addq.w     #imm6u,ri|rj        ; j24%,26,28,30  i=k+1
1001 0111 ##jj ####  subq.w     #imm6u,ri|rj        ; j24%,26,28,30  i=k+1
1001 1000 jjjj j###  move.bit   #0,?adr5[imm3]      ; adr5=0..31
1001 1001 jjjj j###  skipeq.bit #0,?adr5[imm3]      ; adr5=0..31
1001 1010 jjjj j###  move.bit   #1,?adr5[imm3]      ; adr5=0..31
1001 1011 jjjj j###  skipeq.bit #1,?adr5[imm3]      ; adr5=0..31
1001 11ij jjjj iiii  mulu.b     ri,rj,r1|r0         ; i,j=0..31

1011 0##j jjjj ####  move.b     ?adr6,rj            ; adr6=0..63 j=0..31
1011 1##i iiii ####  move.b     ri,?adr6            ; adr6=0..63 i=0..31

1100 #### #### ####  br.w       label

1101 #### #### ####  bsr.w      label

1110 #### jjjj ####  move.b     #imm8,rj            ; j16%..31

1111 00## #### #000  bcs.b      label               ; C=1
1111 00## #### #000  blo.b      label               ; C=1
1111 00## #### #001  beq.b      label               ; Z=1
1111 00## #### #010  bmi.b      label               ; N=1
1111 00## #### #011  bvs.b      label               ; V=1
1111 00## #### #100  blt.b      label               ; S=(N eor V) = 1
1111 00## #### #101  bhcs.b     label               ; H=1
1111 00## #### #110  bts.b      label               ; T=1
1111 00## #### #111  bis.b      label               ; I=1
1111 01## #### #000  bcc.b      label               ; c=0
1111 01## #### #000  bhs.b      label               ; C=0
1111 01## #### #001  bne.b      label               ; Z=0
1111 01## #### #010  bpl.b      label               ; N=0
1111 01## #### #011  bvc.b      label               ; V=0
1111 01## #### #100  bge.b      label               ; S=(N eor V) = 0
1111 01## #### #101  bhcc.b     label               ; H=0
1111 01## #### #110  btc.b      label               ; T=0
1111 01## #### #111  bic.b      label               ; I=0
1111 100j jjjj 0###  move.bit   sr[6],rj[imm3]      ; j=0..31
1111 101j jjjj 0###  move.bit   rj[imm3],sr[6]      ; j=0..31
1111 110j jjjj 0###  skipeq.bit #0,rj[imm3]         ; j=0..31
1111 111j jjjj 0###  skipeq.bit #1,rj[imm3]         ; j=0..31







*******************************************************************
*             example program for STK500  (Mega32)                *
*******************************************************************

        ; connect port B to LED
        
        port_b_dir=$17
        port_b_dat=$18

        move.b  #$ff,r16
        move.b  r16,?port_b_dir
        
        eor.b   r0,r0
        move.b  #$7f,r16
        move.b  #$3f,r17
        move.b  #$1f,r18
        move.b  #$0f,r19

loop:   move.b  r16,?port_b_dat
        move.b  #255,r20
_10:    dec.b   r20
        bne.b   _10
        
        move.b  r17,?port_b_dat
        move.b  #128,r20
_20:    dec.b   r20
        bne.b   _20
        
        move.b  r18,?port_b_dat
        move.b  #64,r20
_30:    dec.b   r20
        bne.b   _30
        
        move.b  r19,?port_b_dat
        move.b  #32,r20
_40:    dec.b   r20
        bne.b   _40
        dec.b   r4
        bne.b   loop
        
        add.b   r16,r16
        addc.b  r0,r16
        add.b   r17,r17
        addc.b  r0,r17
        add.b   r18,r18
        addc.b  r0,r18
        add.b   r19,r19
        addc.b  r0,r19
        
        br.w    loop


Re: Atmel AVR assembler

Quoted text here. Click to load it

I fail to see what's so unusable about the AVR assembler syntax. Your effort
resembles 68000 code. Writing a good assembler takes time, are you writing
it from scratch? I think that's a complete wombat; better invest in learning
the AVR syntax, which is really not that difficult and not unusual.

Also nice for the one that has to maintain your code, long after you've
left. Are you going to write an assembler for every uC or uP come across,
redefining it's assembly language every time?



Re: Atmel AVR assembler

 
Quoted text here. Click to load it

What makes an assembler a "good assembler"? I think a good assembler
should allow you to write bug free code in a minimum of time. And
to do this you don't need a powerful macro system or a high speed
assembler or an integrated development system but you surely need
a well designed instruction syntax. And to write a simple assembler
(without a macro system and which is neither optimized for speed
nor size) isn't a big deal. Yes, you have to spend a few hours to
write the assembler, but this will save you much more time when
you write and debug your assembler programs.
 
Quoted text here. Click to load it

Not every uP I come across, but every uP I have to program in
assembler and which uses an awful syntax like the Intel x86 or
the Atmel AVR (I liked the PDP11 or 68k syntax).

Re: Atmel AVR assembler


Quoted text here. Click to load it

A good assembler should use the mnemonics and rules specified by the
device manufacturer, where there is such a specification. It should
assemble, with the minimum possible modification, code intended for
other assemblers targeting the same part.

An assembler that doesn't follow the device manufacturer's rules is a
very low-level HLL, not an assembler.


Re: Atmel AVR assembler
Quoted text here. Click to load it

Great logic. Let's use a bad design because we then at least
are compatible to the other bad designs! Why not use a superior
design so you are better than all this compatible bad designs?

Quoted text here. Click to load it

I think this is a definition of an assembler which we hadn't here in
a.l.a till now (and we had many different definitions). So, if the
manufacturer decides to change his rules, then all the existing
assemblers becomes a low-level HLL and some low-level HLL's
(which already used the new rules of the manufacturer) becomes
an assembler. A real consistent definition of an assembler.

Re: Atmel AVR assembler


Quoted text here. Click to load it

You're the one with flawed logic here. You say that the vendor's syntax
is hard for you to work with. Fine, write a new language with syntax
that doesn't offend you. But don't call it an AVR assembler. Saying
it's an AVR assembler implies that it assembles AVR assembly language,
the syntax of which was defined by Atmel.

If you're trying to write a Spanish-to-English translator, and you
decide that the syntax of Spanish is inconveniently difficult, and you
wind up writing an Esperanto-to-English translator, well that might be
a useful product in some scenario, but it is not accepting Spanish
input so don't advertise it as such.

What you have written is some kind of pseudo-assembler. It might save a
small amount of time for *you* to work with this tool *alone*, but for
normal AVR users who have to think about maintainability, multi-member
teams, integration with other toolsets, etc. it is a time sink.


Re: Atmel AVR assembler

Quoted text here. Click to load it

Intel *did* write their own assembler. It was called ASM86 (and then ASM286,
and then ASM386). IIRC, they stopped around the 386 version because DOS had
become so ubiquitos as a development platform and MASM was pretty much ASM86
syntax compatible.


Quoted text here. Click to load it

Hmmm...
Last time I checked, Intel hired some computer scientist types to develop
the *assembly language* for the original 8086. Indeed, most of the
complaints I hear from people in this newsgroup about Intel's syntax (type
checking, addressing semantics, etc.), probably exist because they *had*
computer scientists rather than electrical engineers design the syntax :-).

Cheers,
Randy Hyde



Re: Atmel AVR assembler

Quoted text here. Click to load it

Don't see the logic of this statement. Just because they once did have
an assembler doesn't mean that they still sell an assembler. And if
they currently don't have an assembler then they also have no
assembler syntax. Even if Intel would again write it's own assembler,
they couldn't say, this is the only valid assembler syntax for x86
processors.
 

Quoted text here. Click to load it

They can define the language for an "Intel x86 assembler" but
surely not "the" assembly language for the x86. Everybody can
define a syntax for a x86 assembler (not only Intel) and they
are all equal. If we can't ignore (because of the market power)
an awful processor architecture (like Intel X86 or Atmel AVR)
then we at least should ignore the even more awful assembler
syntax used by this companies.

Re: Atmel AVR assembler
[F'up2 reduced to one group --- should have been done earlier.]

Quoted text here. Click to load it




That's quite obviously not what Randall was trying to make it mean,
either.

The fact that Intel actually not only documented an assembly syntax
along with the processor pretty much from the get-go, but even
implemented it themselves as part of marketing the chip, establishes
the fact that there does exist something that doesn't leave us much
chance but to call it "the" standard assembly language for this
processor: that used and published by Intel.  It's quite a broken
design of an assembler, granted, and nobody's expected to like it
particularly --- but it's still the standard syntax.

This standard assembly language for x86 CPUs is also the root of the
entire MASM-compatible family of x86 assembly dialects.  The members
of that family may not all be compatible with each other (although
most can still be switched to actual MASM source compatibility) ---
but they're all roughly compatible to ASM86.  I.e.  you can still feed
assembly source from the original 8086 application notes and data
sheets (or from books from that era) to MASM or one of its derivatives
(running in compatibility mode, where necessary) essentially
unchanged, and expect it to work.  Even "rogue" assemblers like a86
still accept that assembly language, even if they'll grumble a lot
about it.

The only truly independent assembly language family for x86 that I'm
personally aware of is AT&T (including its GNU descendants).
Off-hand, this fundamentally incompatible language looks like a very
bad idea, so it needs to be abandoned or justified.

I think AT&T x86 assembler language makes a whole lot more sense than
Intel's ever did.  Not because of the oft-maligned opposite order of
source and destination operand, mind you, but because it puts the
definition of operation width where it belongs (as a letter in the
opcode) instead of where it has to be second-guessed (by inspecting
stuff like BYTE PTR [whatever]).  The price to be paid for this
improvement of the syntax was a loss of direct access to the entire
body of pre-existing assembly source.  AT&T deemed that acceptible,
probably because they didn't plan on using their 'as' on any
third-party original assembler sources anyway, and the compiler
doesn't care what language it emits.

The main problem with Intel syntax IMHO is that they were trying to
let the assembler do half the linker's and a good part of the human's
job on top of that of a genuine assembler.  Frankly, if the human
programmer has to look at more than one line of source code (setting
aside macros) to figure out which actual opcode a given line of
assembly code will generate, something's seriously wrong with that
assembler.  Once they had added BYTE PTR [] and ASSUME to the
language, the damage was irreversible.

--
Hans-Bernhard Broeker ( snipped-for-privacy@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.

Re: Atmel AVR assembler

 
 
| > What makes an assembler a "good assembler"? I think a good assembler
| > should allow you to write bug free code in a minimum of time. And
 
| A good assembler should use the mnemonics and rules specified by the
| device manufacturer, where there is such a specification. It should
| assemble, with the minimum possible modification, code intended for
| other assemblers targeting the same part.
 
| An assembler that doesn't follow the device manufacturer's rules is a
| very low-level HLL, not an assembler.

I can't agree,
CPU/MC-producers actually don't care about sense-making mnemonics.

And like Herbert, I also use 'my very own' syntax to at least try to
cover all MC/CPU I ever worked on with one cross-compatible language.

Of course, x86-coders are not familiar with Herbert's 68000 styled
or my Zilog-styled syntax. Therefore I use it only personal and don't
try to make it a public need.

But Herbert's conversion is pure logical based, even I use hardware
ordered register-numbers and have the size-casts in/at the operands.

__
wolfgang



Re: Atmel AVR assembler


Quoted text here. Click to load it

That's probably true but irrelevant. Assembly language is defined by
the CPU vendor. Anything you do that deviate from the vendor's spec is
writing a new language.

This is a semantic issue. I can't call the OP's product an assembler
because although what goes in looks like assembly language, it is not
in fact assembly language for any known processor.


Re: Atmel AVR assembler
Op 23 Jul 2005 11:29:27 -0700 schreef snipped-for-privacy@larwe.com:

Quoted text here. Click to load it

You've nevwe programmed in Forth, did you?
An assembler in Forth can use the same syntax as a 'normal' assembler, by
using the order: opcode, destiny, source like (I assume) the one of AVR
does. But it is simpler to implement, and easier to understand (for a Forth
programmer) in the order: source, destiny, opcode. Postfix so to speak.
I know lots of people that use this syntax and they can program each and
every program with it.

Coos
--
CHForth, 16 bit DOS applications
http://home.hccnet.nl/j.j.haak/forth.html

Re: Atmel AVR assembler
Quoted text here. Click to load it

So by your definition of syntax equivalency, Yoda speaks normal
English?


Re: Atmel AVR assembler

 
| > I can't agree,
| > CPU/MC-producers actually don't care about sense-making mnemonics.
|
| That's probably true but irrelevant. Assembly language is defined by
| the CPU vendor. Anything you do that deviate from the vendor's spec is
| writing a new language.

That's new to me, AT&T/gas/gcc/.. use Intel/AMD recommeded style?
 
| This is a semantic issue. I can't call the OP's product an assembler
| because although what goes in looks like assembly language, it is not
| in fact assembly language for any known processor.

There are that many ASM-dialects around, that any attempt to create
one more logical syntax count for itself, regardless of portability.  
I'm not familiar with Herbert's way either, but I can see the idea.

If you like to see a few options of my disassembler:

http://web.utanet.at/schw1285/KESYS/index.htm ,[codesnips],[HEXTUTOR]

__
wolfgang



Re: Atmel AVR assembler

Quoted text here. Click to load it


No.  But I'm willing to forgive AT&T (and GNU, which borrowed their
syntax) this violation of a well-founded principle, on the grounds
that Intel's original x86 assembly language is so incredibly horrible.

Actually, there are only two real dialects of x86 assembly these days:
MASM (MS's implementation of the original Intel syntax), and gas.  All
other assemblers that want a noticeable share of the market strive to
emulate either of these to the letter.

--
Hans-Bernhard Broeker ( snipped-for-privacy@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.

Re: Atmel AVR assembler

Quoted text here. Click to load it

Absurd.

See this:

< http://retroforth.org/asmchart/

All of the actual Assembler branch from NASM, plus, a little
bit of inspiration from TASM (concerning FASM), and from A86
(concerning RosAsm, and maybe, GoAsm).

None of the actual Assemblers Authors would be stupid enough
for "striving to emulate" anything like MASM.


Betov.

< http://rosasm.org




Re: Atmel AVR assembler


[about assembler syntax]

| > That's new to me, AT&T/gas/gcc/.. use Intel/AMD recommended style?
 
| No.  But I'm willing to forgive AT&T (and GNU, which borrowed their
| syntax) this violation of a well-founded principle, on the grounds
| that Intel's original x86 assembly language is so incredibly horrible.

This AT&T solution is absolutely not well suited for x86 processors,
it's weird and confusing and far away from explaining an operation.
Just read all the FAQ's on it.
 
| Actually, there are only two real dialects of x86 assembly these days:
| MASM (MS's implementation of the original Intel syntax), and gas.  All
| other assemblers that want a noticeable share of the market strive to
| emulate either of these to the letter.

Yes, the market share ... and MASM as the Windoze/C-side tool.
But as we last few pure ASM-coders here in A.L.A see and use many
things far beyond the M$-world imagination, we aren't bound to it.
How will MASM rank within C+/-..?, I think less than one per million.

btw: FASM/NASM seem to be the most used by ASM-newbies recently,
you may say this are only a handful, but the ASM-population grows daily.

__
wolfgang kern (Author of KESYS)
  How fast and short could windoze be
  if everyone would think like me.
http://web.utanet.at/schw1285/KESYS/index.htm


Re: Atmel AVR assembler
@newsreader1.utanet.at:

Quoted text here. Click to load it

Indead. I regulary take a look at all Assemblers Boards,
and the number of Posts, for example, at FASM Board, is
now beating the number of MASM Board Posts.

Also, considering that there is, so to say, no real Asmers
using MASM (99% of them are HLL Programmers making occasional
use of MASM for HLLs' enhancements...), and that most of FASM
users are real Asmers doing real things (like the MenuetOS
developers, and such...), the real growing rate of the real
"ASM-population", is quite encouraging.

:)

Betov.

< http://rosasm.org



Re: Atmel AVR assembler
Quoted text here. Click to load it

Actually the rationale for gas is even simpler.  It is based on the
requirements for an assembler for gcc, which at one point required
a suitable ordering of operands and means of specifying actual
opcodes.  It was developed with what amounts to apologies because
of those needs, gcc being less capable of adapting than most
humans.

Many of the convolutions of MASM can be blamed on the abysmally
complex object code format, which was imposed by Intel way back
when.  As usual Microsoft took that and misapplied it, while adding
their own incompatabilities.  That object format is now largely
forgotten, but the effects are still here.

--
Chuck F ( snipped-for-privacy@yahoo.com) ( snipped-for-privacy@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
We've slightly trimmed the long signature. Click to see the full one.
Re: Atmel AVR assembler


Quoted text here. Click to load it


Last time I counted, there were about a half-dozen different dialects of x86
assembly language. I don't know how you define "real", but assemblers like
NASM, FASM, GoAsm, TASM, MASM, Gas/ATT, Gas/Intel, and HLA all have fairly
decent followings (numbering in the thousands of users, each).  Granted,
MASM (because of its 20-year history) has the largest market share, by far,
but the others are growing and cutting into that market share.  Particularly
as people move away from using the Windows platform.
Cheers,
Randy Hyde



Site Timeline