Hi folks,
I'm routing a board which will be tested by an ATE system (Bottom Access). The questions are:
1) VIA FORM FACTOR Let's suppose I have a net on the TOP layer and I need to test it: I have to add a VIA. Are there any rules about the form factor of the VIA? I'm talking about the hole diameter, the pad diameter on TOP, the pad diameter on BOTTOM2) NETS TO TEST Let's suppose I have a 19-wire bus that connect the CPU to some external RAM memory. No passive components in the middle. Do I need to add a test point on these wire?
3) DESIGN FOR TESTABILITY DOCS Are there any standard documents explaining how to route an ATE-ready board?thanks for any help, Enrico