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ATA/ATAPI-5 Question

I'm working with the Cirrus Logic EP9315, Arm920T Core, currently working on my IDE interface routines.

I have the basic communication with the hard drive working, I can get the identify information, read/write data, all seems to work fine. Using PIO Mode 4, the drive is an older 6 gig drive so which does not implement the Packet command set.

Here's the problem though...

When I send the writesectors command, and specify more than 1 sector, sometimes the drive will stay busy indefinitely (currently not sure about error status, I'll look into that next).

If I only use 1 sector, this never happens. The drive also sounds differently.

When creating my file system, I can hear the heads move to the next available block as it creates the block headers. When I write 2 sectors at once, this does not happen.

Either case however, there is no error!!!!

Anyone have any idea as to what could be wrong?

Thanks,

Stephan

Reply to
Stephan Rose
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Stephan Rose wrote in news: snipped-for-privacy@4ax.com:

Nor will newer drives. Packet commands are for optical drives.

Be sure the disk is not BSY and DRDY is set (read the Status register for these to clear any pending INTRQ assertion), then program the sector count register, start LBA (be sure the LBA mode and device select bits are set correctly) and then issue the WRITE SECTOR command. Remember a count of zero means the MTU of 256 sectors. Now wait for DRQ and then read until DRQ is no more (cross check with a count of interface reads).

Remember that in modes above PIO Mode 2 you must honor the IORDY handshake signal. Also, try enabling the interrupt assertion in Device Control by setting the NIEN bit to zero. Then poll for INTRQ assertion, read a sector, poll for INTRQ assertion, read a sector, etc. The ATA spec. says that a (working) drive must clear BSY within 31 seconds of command issue. If this is not the case then the drive is broken.

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Reply to
Mark A. Odell

One other thing you might want to check is which register you are reading. I worked with older drivers but... There were two registers, a primary status register and an alternate status register. The alternate register was there to allow you to poll driver status and would not clear status bits. The primary register would clear various status bits when ready.. If you polled the primary register, it was possible to confuse the state machine by reading and clearing states it thought were set, making the driver idle and busy, an illegal and undefined state. If you used interrupts or DMA, you were safe. Hope this helps,

Reply to
Jim Brooks

"Jim Brooks" wrote in news:SAMuc.634631$Ig.167792@pd7tw2no:

Just the assertion of the INTRQ# signal line an the DF bit of the status reg.

I'm not sure I've ever seen this happen nor does the spec. describe this possibility. However, polled mode, the Alternate Status register is the correct register to read.

Top-posting sure destroys the thread, eh?

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Reply to
Mark A. Odell

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