Hey folks , i need ur opinion about something : To implement an AES decryption (CBC mode ) algorithm in ASIC , what would be the best way to do it ? i mean among these architectures which one do you choose and why :
- Basic iterative architecture
- Partial loop unrolling
- full loop unrolling
- Partia outer-round pipelining
- Full outerround pipelining
- Inner-round pipelining
- Partial mixed innerand outerroundpipelining
- Full mixed inner- and outer-round pipelining
- other ...